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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
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Spartan-6 FPGA Electrical Characteristics
Spartan(R)-6 LX FPGAs are available in -3, -2, and -1L speed grades, with -3 having the highest performance. Spartan-6 LXT FPGAs are available in -4, -3, and -2 speed grades, with -4 having the highest performance. Spartan-6 FPGA DC and AC characteristics are specified for both commercial and industrial grades. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -2 speed grade industrial device are the same as for a -2 speed grade commercial device). However, only selected speed grades and/or devices might be available in the industrial range. The -3N speed grade, designated for Spartan-6 devices that do not support memory controller block (MCB) functionality, has identical timing characteristics to the -3 speed grade. All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Spartan-6 FPGA data sheet, part of an overall set of documentation on the Spartan-6 family of FPGAs, is available on the Xilinx website. All specifications are subject to change without notice.
Spartan-6 FPGA DC Characteristics
Table 1: Absolute Maximum Ratings (1)
Symbol
VCCINT VCCAUX VCCO VBATT VFS VREF
Description
Internal supply voltage relative to GND Auxiliary supply voltage relative to GND Output drivers supply voltage relative to GND Key memory battery backup supply (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) External voltage supply for eFUSE programming (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only)(2) Input reference voltage DC Commercial 20% overshoot duration All user and dedicated I/Os Industrial I/O input voltage or voltage applied to 3-state output, relative to GND(4) Restricted to maximum of 100 user I/Os Industrial 8% overshoot DC 20% overshoot duration 4% overshoot duration(5) 20% overshoot duration Commercial 15% overshoot duration(5) 10% overshoot duration 20% overshoot duration 10% overshoot duration 8% overshoot duration(5) duration(5) -0.5 to 1.32 -0.5 to 3.75 -0.5 to 3.75 -0.5 to 4.05 -0.5 to 3.75 -0.5 to 3.75 -0.60 to 4.10 -0.75 to 4.25 -0.75 to 4.40 -0.60 to 3.95 -0.75 to 4.15 -0.75 to 4.40 -0.75 to 4.35 -0.75 to 4.40 -0.75 to 4.45 -0.75 to 4.25 -0.75 to 4.35 -0.75 to 4.40
Units
V V V V V V V V V V V V V V V V V V
VIN and VTS(3)
(c) 2009-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 1: Absolute Maximum Ratings (1) (Cont'd)
Symbol
TSTG
Description
Storage temperature (ambient) Maximum soldering (TQG144, CPG196, CSG225, CSG324, CSG484, and FTG256) temperature(6) -65 to 150 +260 +250 +220 +125
Units
C C C C C
TSOL
Maximum soldering temperature(6) (Pb-free packages: FGG484, FGG676, and FGG900) Maximum soldering temperature(6) (Pb packages: FT256, FG484, FG676, and FG900) Maximum junction temperature(6)
Tj
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. 2. When programming eFUSE, VFS VCCAUX. Requires up to 40 mA current. For read mode, VFS can be between GND and 3.45 V. 3. I/O absolute maximum limit applied to DC and AC signals. Overshoot duration is the percentage of a data period that the I/O is stressed beyond 3.45V. 4. For I/O operation, refer to the Spartan-6 FPGA SelectIO Resources User Guide. 5. Maximum percent overshoot duration to meet 4.40V maximum. 6. For soldering guidelines and thermal considerations, see Spartan-6 FPGA Packaging and Pinout Specification.
Table 2: Recommended Operating Conditions(1)
Symbol Description
Internal supply voltage relative to GND, Tj = 0C to +85C VCCINT
Temperature Range
Commercial
Speed Grade
-4, -3, -2
Memory Controller Block(2) Performance
standard extended
Min
1.14 1.2 0.95 1.14 1.2 0.95
Typ
1.2 1.23 1.0 1.2 1.23 1.0
Max
1.26 1.26 1.05 1.26 1.26 1.05
Units
V V V V V V
-1L Internal supply voltage relative to GND, Tj = -40C to +100C Industrial -3, -2
standard standard extended
-1L Auxiliary supply voltage relative to GND when VCCAUX = 2.5V, Tj = 0C to +85C Auxiliary supply voltage relative to GND when VCCAUX = 2.5V, Tj = -40C to +100C Auxiliary supply voltage relative to GND when VCCAUX = 3.3V, Tj = 0C to +85C Auxiliary supply voltage relative to GND when VCCAUX = 3.3V, Tj = -40C to +100C Output supply voltage relative to GND, Tj = 0C to +85C Output supply voltage relative to GND, Tj = -40C to +100C Input voltage relative to GND, Tj = 0C to +85C Input voltage relative to GND, Tj = -40C to +100C Input voltage relative to GND, PCI I/O standard, Tj = 0C to +85C Input voltage relative to GND, PCI I/O standard, Tj = -40C to +100C Commercial Industrial -4, -3, -2, -1L -3, -2, -1L
standard N/A N/A
2.375
2.5
2.625
V
VCCAUX(3)
Commercial Industrial
-4, -3, -2, -1L -3, -2, -1L
N/A N/A 3.15 3.3 3.45 V
Commercial Industrial Commercial Industrial Commercial Industrial
VCCO(4)(5)(6)
-4, -3, -2, -1L -3, -2, -1L -4, -3, -2, -1L -3, -2, -1L -4, -3, -2, -1L(7) -3, -2, -1L(7)
N/A N/A N/A N/A N/A N/A 1.1 - 3.45 V
-0.5 -0.5 -0.5 -0.5
- - - -
4.0 3.95 VCCO + 0.5 VCCO + 0.5
V V V V
VIN
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 2: Recommended Operating Conditions(1) (Cont'd)
Symbol Description
Maximum current through pin using PCI I/O standard when forward biasing the clamp diode.
Temperature Range
Commercial Industrial Commercial
Speed Grade
-4, -3, -2, -1L(7) -3, -2, -1L(7) -4, -3, -2, -1L
Memory Controller Block(2) Performance
N/A N/A N/A
Min
Typ
Max
Units
- -
- -
10 10
mA mA
IIN(8)
VBATT(9)
Battery voltage relative to GND, Tj = 0C to +85C (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) Battery voltage relative to GND, Tj = -40C to +100C (XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only)
Industrial
-3, -2, -1L
N/A
1.0
-
3.6
V
Notes: 1. All voltages are relative to ground. 2. See Interface Performances for Memory Interfaces in Table 25. The standard VCCINT voltage range applies to designs not using an MCB, or to devices that do not support MCB functionality including the LX4 device, the TQG144 and CPG196 packages, and the -3N speed grade. 3. Recommended maximum voltage droop for VCCAUX is 10 mV/ms. 4. Configuration data is retained even if VCCO drops to 0V. 5. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. 6. For PCI systems, the transmitter and receiver should have common supplies for VCCO. 7. Devices with a -1L speed grade do not support Xilinx PCI IP. 8. Do not exceed a total of 100 mA per bank. 9. VBATT is required to maintain the battery backed RAM (BBR) AES key when VCCAUX is not applied. Once VCCAUX is applied, VBATT can be unconnected. When BBR is not used, Xilinx recommends connecting to VCCAUX or GND. However, VBATT can be unconnected.
Table 3: eFUSE Programming Conditions(1)
Symbol
VFS(2) IFS VCCAUX VCCINT tj External voltage supply VFS supply current Auxiliary supply voltage relative to GND
Description
Min
3.2 - 3.2 1129 1.14 15
Typ
3.3 - 3.3 1140 1.2 -
Max
3.4 40 3.45 1151 1.26 85
Units
V mA V V C
RFUSE(3) External resistor from RFUSE pin to GND Internal supply voltage relative to GND Temperature range
Notes: 1. These specifications apply during programming of the eFUSE AES key. Programming is only supported through JTAG.The AES key is only supported in the following devices: XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T. 2. When programming eFUSE, VFS must be less than or equal to VCCAUX. When not programming or when eFUSE is not used, Xilinx recommends connecting VFS to GND. However, VFS can be between GND and 3.45 V. 3. An RFUSE resistor is required when programming the eFUSE AES key. When not programming or when eFUSE is not used, Xilinx recommends connecting the RFUSE pin to VCCAUX or GND. However, RFUSE can be unconnected.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 4: DC Characteristics Over Recommended Operating Conditions
Symbol
VDRINT VDRAUX IREF IL
Description
Data retention VCCINT voltage (below which configuration data might be lost) Data retention VCCAUX voltage (below which configuration data might be lost) VREF leakage current per pin Input or output leakage current per pin (sample-tested) Leakage current on pins during hot socketing with FPGA unpowered Die input capacitance at the pad Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V or VCCAUX = 3.3V Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V or VCCAUX = 2.5V All pins except PROGRAM_B, DONE, and JTAG pins when HSWAPEN = 1 PROGRAM_B, DONE, and JTAG pins, or other pins when HSWAPEN = 0
Min
0.8 2.0 -10 -10 -20
Typ
- - - - - IHS + IRPU
Max
- - 10 10 20
Units
V V A A A A
IHS
CIN
- 200 120 60 40 12 200 140 - - 23 39 56
- - - - - - - - - 100 25 50 75
10 500 350 200 150 100 550 400 150 - 55 72 109
pF A A A A A A A nA
IRPU
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V Pad pull-down (when selected) @ VIN = VCCO, VCCAUX = 3.3V Pad pull-down (when selected) @ VIN = VCCO, VCCAUX = 2.5V Battery supply current Resistance of optional input differential termination circuit, VCCAUX = 3.3V Thevenin equivalent resistance of programmable input termination (UNTUNED_SPLIT_25)
IRPD IBATT(1) RDT
(2)
RIN_TERM(4)
Thevenin equivalent resistance of programmable input termination (UNTUNED_SPLIT_50) Thevenin equivalent resistance of programmable input termination (UNTUNED_SPLIT_75)
Notes: 1. Maximum value specified for worst case process at 25C. XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only. 2. Refer to IBIS models for RDT variation and for values at VCCAUX = 2.5V. 3. VCCO2 is not required for data retention. The minimum VCCO2 for power-on reset and configuration is 1.65V. 4. Termination resistance to a VCCO/2 level.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Quiescent Current
Typical values for quiescent supply current are specified at nominal voltage, 25C junction temperatures (Tj). Quiescent supply current is specified by speed grade for Spartan-6 devices. Xilinx recommends analyzing static power consumption using the XPOWERTM Estimator (XPE) tool (download at http://www.xilinx.com/power) for conditions other than those specified in Table 5. Table 5: Typical Quiescent Supply Current
Symbol
ICCINTQ
Description
Quiescent VCCINT supply current
Device
XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T
Speed Grade -4
N/A N/A N/A N/A 11.0 N/A 15.0 N/A 29.0 N/A 36.0 N/A 51.0 N/A N/A N/A N/A 2.0 N/A 3.0 N/A 4.0 N/A 5.0 N/A 7.0
-3
4.0 4.0 6.0 11.0 11.0 15.0 15.0 29.0 29.0 36.0 36.0 51.0 51.0 1.0 1.0 2.0 2.0 2.0 3.0 3.0 4.0 4.0 5.0 5.0 7.0 7.0
-2
4.0 4.0 6.0 11.0 11.0 15.0 15.0 29.0 29.0 36.0 36.0 51.0 51.0 1.0 1.0 2.0 2.0 2.0 3.0 3.0 4.0 4.0 5.0 5.0 7.0 7.0
-1L
2.4 2.4 4.0 6.6 N/A 9.0 N/A 17.4 N/A 21.6 N/A 31.0 N/A 1.0 1.0 2.0 2.0 N/A 3.0 N/A 4.0 N/A 5.0 N/A 7.0 N/A
Units
mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
ICCOQ
Quiescent VCCO supply current
XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 5: Typical Quiescent Supply Current (Cont'd)
Symbol
ICCAUXQ
Description
Quiescent VCCAUX supply current
Device
XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T
Speed Grade -4
N/A N/A N/A N/A 4.0 N/A 5.0 N/A 7.0 N/A 9.0 N/A 12.0
-3
2.5 2.5 3.0 4.0 4.0 5.0 5.0 7.0 7.0 9.0 9.0 12.0 12.0
-2
2.5 2.5 3.0 4.0 4.0 5.0 5.0 7.0 7.0 9.0 9.0 12.0 12.0
-1L
2.5 2.5 3.0 4.0 N/A 5.0 N/A 7.0 N/A 9.0 N/A 12.0 N/A
Units
mA mA mA mA mA mA mA mA mA mA mA mA mA
Notes: 1. Typical values are specified at nominal voltage, 25C junction temperatures (Tj). Industrial (I) grade devices have the same typical values as commercial (C) grade devices at 25C, but higher values at 100C. Use the XPE tool to calculate 100C values. 2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. 3. If differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools.
Table 6: Power Supply Ramp Time
Symbol
VCCINTR VCCO2(1) VCCAUXR
Description
Internal supply voltage ramp time
Speed Grade
-4, -3, -2 -1L
Ramp Time
0.20 to 50.0 0.20 to 40.0 0.20 to 50.0 0.20 to 50.0
Units
ms ms ms ms
Output drivers bank 2 supply voltage ramp time Auxiliary supply voltage ramp time
All All
Notes: 1. The minimum VCCO2 for power-on reset and configuration is 1.65V 2. Spartan-6 FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply. Use the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools to estimate current drain on these supplies. Spartan-6 devices do not have a required power-on sequence.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
SelectIOTM Interface DC Input and Output Levels
Table 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
I/O Standard
LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS18_JEDEC LVCMOS15 LVCMOS15_JEDEC LVCMOS12 LVCMOS12_JEDEC PCI33_3(2) PCI66_3(2) I2C SMBUS SDIO MOBILE_DDR HSTL_I HSTL_II HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL3_I SSTL3_II SSTL2_I SSTL2_II SSTL18_I SSTL18_II SSTL15_II Notes:
1. 2. VCCO range required when using I/O standard for an output. Also required for PCI33_3, LVCMOS18_JEDEC, LVCMOS15_JEDEC, and LVCMOS12_JEDEC inputs, and for LVCMOS25 inputs when VCCAUX = 3.3V. For PCI systems, the transmitter and receiver should have common supplies for VCCO.
VCCO for Drivers(1) V, Min
3.0 3.0 2.3 1.65 1.65 1.4 1.4 1.1 1.1 3.0 3.0 2.7 2.7 3.0 1.7 1.4 1.4 1.4 1.7 1.7 1.7 3.0 3.0 2.3 2.3 1.7 1.7 1.425
VREF for Inputs V, Max
3.45 3.45 2.7 1.95 1.95 1.6 1.6 1.3 1.3 3.45 3.45 3.45 3.45 3.45 1.9 1.6 1.6 1.6 1.9 1.9 1.9 3.45 3.45 2.7 2.7 1.9 1.9 1.575 0.68 0.68 - 0.8 - - 1.3 1.3 1.13 1.13 0.833 0.833 0.69 0.75 0.75 0.9 0.9 0.9 1.1 1.5 1.5 1.25 1.25 0.9 0.9 0.75 0.9 0.9 - 1.1 - - 1.7 1.7 1.38 1.38 0.969 0.969 0.81 VREF is not used for these I/O standards
V, Nom
3.3 3.3 2.5 1.8 1.8 1.5 1.5 1.2 1.2 3.3 3.3 3.0 3.0 3.3 1.8 1.5 1.5 1.5 1.8 1.8 1.8 3.3 3.3 2.5 2.5 1.8 1.8 1.5
V, Min
V, Nom
V, Max
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 8: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
I/O Standard
LVDS_33 LVDS_25 BLVDS_25 MINI_LVDS_33 MINI_LVDS_25 LVPECL_33(1) LVPECL_25 RSDS_33 RSDS_25 TMDS_33(1) PPDS_33 PPDS_25 DISPLAY_PORT DIFF_MOBILE_DDR DIFF_HSTL_I DIFF_HSTL_II DIFF_HSTL_III DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 DIFF_SSTL3_I DIFF_SSTL3_II DIFF_SSTL2_I DIFF_SSTL2_II DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL15_II Notes:
1. LVPECL_33 and TMDS_33 inputs require VCCAUX = 3.3V nominal.
VCCO for Drivers V, Min
3.0 2.25 2.25 3.0 2.25
V, Nom
3.3 2.5 2.5 3.3 2.5 N/A-Inputs Only N/A-Inputs Only
V, Max
3.45 2.75 2.75 3.45 2.75
3.0 2.25 3.14 3.0 2.25 2.3 1.7 1.4 1.4 1.4 1.7 1.7 1.7 3.0 3.0 2.3 2.3 1.7 1.7 1.425
3.3 2.5 3.3 3.3 2.5 2.5 1.8 1.5 1.5 1.5 1.8 1.8 1.8 3.3 3.3 2.5 2.5 1.8 1.8 1.5
3.45 2.75 3.45 3.45 2.75 2.7 1.9 1.6 1.6 1.6 1.9 1.9 1.9 3.45 3.45 2.7 2.7 1.9 1.9 1.575
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics In Table 9 and Table 10, values for VIL and VIH are recommended input voltages. Values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 9: Single-Ended I/O Standard DC Input and Output Levels
I/O Standard
LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS18 (-1L) LVCMOS18_JEDEC LVCMOS15 LVCMOS15 (-1L) LVCMOS15_JEDEC LVCMOS12 LVCMOS12 (-1L) LVCMOS12_JEDEC PCI33_3 PCI66_3 I2C SMBUS SDIO MOBILE_DDR HSTL_I HSTL_II HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL3_I SSTL3_II SSTL2_I SSTL2_II SSTL18_I SSTL18_II SSTL15_II
VIL V, Min
-0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5
VIH V, Max
0.8 0.8 0.7 0.38 0.33
VOL V, Max
4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 VCCO + 0.5 VCCO + 0.5 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1 4.1
VOH V, Min
2.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.45 VCCO - 0.45 VCCO - 0.45 75% VCCO 75% VCCO 75% VCCO VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 90% VCCO 90% VCCO - - 75% VCCO 90% VCCO VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VTT + 0.6 VTT + 0.8 VTT + 0.61 VTT + 0.81 VTT + 0.47 VTT + 0.60 VTT + 0.4
IOL mA
Note(2) Note(2) Note(2) Note(2) Note(2) Note(2) Note(3) Note(3) Note(3) Note(4) Note(4) Note(4) 1.5 1.5 3 4 0.1 0.1 8 16 24 11 22 30 8 16 8.1 16.2 6.7 13.4 13.4
IOH mA
Note(2) Note(2) Note(2) Note(2) Note(2) Note(2) Note(3) Note(3) Note(3) Note(4) Note(4) Note(4) -0.5 -0.5 - - -0.1 -0.1 -8 -16 -8 -11 -22 -11 -8 -16 -8.1 -16.2 -6.7 -13.4 -13.4
V, Min
2.0 2.0 1.7 0.8 0.71 65% VCCO 0.8 0.71 65% VCCO 0.8 0.71 65% VCCO 50% VCCO 50% VCCO 70% VCCO 2.1 75% VCCO 80% VCCO VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.2 VREF + 0.2 VREF + 0.15 VREF + 0.15 VREF + 0.125 VREF + 0.125 VREF + 0.1
V, Max
0.4 0.4 0.4 0.45 0.45 0.45 25% VCCO 25% VCCO 25% VCCO 0.4 0.4 0.4 10% VCCO 10% VCCO 20% VCCO 0.4 12.5% VCCO 10% VCCO 0.4 0.4 0.4 0.4 0.4 0.4 VTT - 0.6 VTT - 0.8 VTT - 0.61 VTT - 0.81 VTT - 0.47 VTT - 0.60 VTT - 0.4
35% VCCO 0.38 0.33 35% VCCO 0.38 0.33 35% VCCO 30% VCCO 30% VCCO 25% VCCO 0.8 12.5% VCCO 20% VCCO VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.1 VREF - 0.2 VREF - 0.2 VREF - 0.15 VREF - 0.15 VREF - 0.125 VREF - 0.125 VREF - 0.1
Notes: 1. Tested according to relevant specifications. 2. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA. 3. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA. 4. Using drive strengths of 2, 4, 6, 8, or 12 mA. 5. For more information, refer to the Spartan-6 FPGA SelectIO Resources User Guide.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 10: Differential I/O Standard DC Input and Output Levels
VID VICM mV, Max
600 600 - 600 600 1000 1000 - - 1200 400 400 1260 - - - - - - - - - - - - - -
VOD mV, Min
247 247 240 300 300
VOCM mV, Max
454 454 460 600 600
VOH V, Max
1.375 1.375
VOL V, Max
- - - - -
I/O Standard
LVDS_33 LVDS_25 BLVDS_25 MINI_LVDS_33 MINI_LVDS_25 LVPECL_33 LVPECL_25 RSDS_33 RSDS_25 TMDS_33 PPDS_33 PPDS_25 DISPLAY_PORT DIFF_MOBILE_DDR DIFF_HSTL_I DIFF_HSTL_II DIFF_HSTL_III DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 DIFF_SSTL3_I DIFF_SSTL3_II DIFF_SSTL2_I DIFF_SSTL2_II DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL15_II Notes:
1.
mV, Min
100 100 100 200 200 100 100 100 100 150 100 100 190 100 100 100 100 100 100 100 100 100 100 100 100 100 100
V, Min
0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 2.7 0.2 0.2 0.3 0.78 0.68 0.68 0.68 0.8 0.8 0.8 1.0 1.0 1.0 1.0 0.7 0.7 0.55
V, Max
2.35 2.35 2.35 1.95 1.95 2.8(1) 1.95 1.5 1.5 3.23(1) 2.3 2.3 2.35 1.02 0.9 0.9 0.9 1.1 1.1 1.1 1.9 1.9 1.5 1.5 1.1 1.1 0.95
V, Min
1.125 1.125
V, Min
- - - - -
Typical 50% VCCO 1.0 1.0 1.4 1.4 Inputs only Inputs only
100 100 400 100 100 - - - - - - - - - - - - - - -
400 400 800 400 400 - - - - - - - - - - - - - - -
1.0 1.0
1.4 1.4
- - - - - -
- - - - - -
VCCO - 0.405 VCCO - 0.190 0.5 0.5 1.4 1.4
Typical 50% VCCO - - - - - - - - - - - - - - - - - - - - - - - - - - - -
90% VCCO 10% VCCO VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VCCO - 0.4 VTT + 0.6 VTT + 0.8 0.4 0.4 0.4 0.4 0.4 0.4 VTT - 0.6 VTT - 0.8
VTT + 0.61 VTT - 0.61 VTT + 0.81 VTT - 0.81 VTT + 0.47 VTT - 0.47 VTT + 0.6 VTT + 0.4 VTT - 0.6 VTT - 0.4
LVPECL_33 and TMDS_33 maximum VICM is the lower of V (maximum) or VCCAUX - (VID/2)
eFUSE Read Endurance
Table 11 lists the minimum guaranteed number of read cycle operations for Device DNA and for the AES eFUSE key. For more information, see the Spartan-6 FPGA Configuration User Guide. Table 11: eFUSE Read Endurance
Symbol
DNA_CYCLES AES_CYCLES
Description
Number of DNA_PORT READ operations or JTAG ISC_DNA read command operations. Unaffected by SHIFT operations. Number of JTAG FUSE_KEY or FUSE_CNTL read command operations. Unaffected by SHIFT operations.
Speed Grade -4 -3 -2 -1L
Units (Min)
Read Cycles Read Cycles
30,000,000 30,000,000
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
GTP Transceiver Specifications
GTP transceivers are available in the Spartan-6 LXT family of devices. See DS160: Spartan-6 Family Overview for more information.
GTP Transceiver DC Characteristics
Table 12: Absolute Maximum Ratings for GTP Transceivers(1)
Symbol
MGTAVCC MGTAVTTTX MGTAVTTRX MGTAVCCPLL MGTAVTTRCAL VIN VMGTREFCLK
Description
Analog supply voltage for the GTP transmitter and receiver circuits relative to GND Analog supply voltage for the GTP transmitter termination circuit relative to GND Analog supply voltage for the GTP receiver termination circuit relative to GND Analog supply voltage for the GTP transmitter and receiver PLL circuits relative to GND Analog supply voltage for the resistor calibration circuit of the GTP transceiver bank (top or bottom) Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage Reference clock absolute input voltage
MIn
-0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -0.5
Max
1.32 1.32 1.32 1.32 1.32 1.32 1.32
Units
V V V V V V V
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Table 13: Recommended Operating Conditions for GTP Transceivers(1)(2)(3)
Symbol
MGTAVCC MGTAVTTTX MGTAVTTRX MGTAVCCPLL MGTAVTTRCAL
Description
Analog supply voltage for the GTP transmitter and receiver circuits relative to GND Analog supply voltage for the GTP transmitter termination circuit relative to GND Analog supply voltage for the GTP receiver termination circuit relative to GND Analog supply voltage for the GTP transmitter and receiver PLL circuits relative to GND Analog supply voltage for the resistor calibration circuit of the GTP transceiver bank (top or bottom)
Min
1.14 1.14 1.14 1.14 1.14
Typ
1.20 1.20 1.20 1.20 1.20
Max
1.26 1.26 1.26 1.26 1.26
Units
V V V V V
Notes: 1. Each voltage listed requires the filter circuit described in Spartan-6 FPGA GTP Transceivers User Guide. 2. Voltages are specified for the temperature range of Tj = -40C to +100C. 3. The voltage level of MGTAVCCPLL must not exceed the voltage level of MGTAVCC +10mV. The voltage level of MGTAVCC must not exceed the voltage level of MGTAVCCPLL.
Table 14: GTP Transceiver Current Supply (per Lane)
Symbol
IMGTAVCC IMGTAVTTTX IMGTAVTTRX IMGTAVCCPLL RMGTRREF
Description
GTP transceiver internal analog supply current GTP transmitter termination supply current GTP receiver termination supply current GTP transmitter and receiver PLL supply current Precision reference resistor for internal calibration termination
Typ(1)
40.4 27.4 13.6 28.7
Max
Units
mA
Note 2
mA mA mA
50.0 1% tolerance
Notes: 1. Typical values are specified at nominal voltage, 25C, with a 2.5 Gb/s line rate, with a shared PLL use mode. 2. Values for currents of other transceiver configurations and conditions can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 15: GTP Transceiver Quiescent Supply Current (per Lane)(1)(2)(3)(4)
Symbol
IMGTAVCCQ IMGTAVTTTXQ IMGTAVTTRXQ
Description
Quiescent MGTAVCC supply current Quiescent MGTAVTTTX supply current Quiescent MGTAVTTRX supply current
Typ(5)
1.7 0.1 1.2 1.0
Max
Units
mA
Note 2
mA mA mA
IMGTAVCCPLLQ Quiescent MGTAVCCPLL supply current
Notes: 1. Device powered and unconfigured. 2. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools. 3. GTP transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTP transceivers. 4. Does not include power-up MGTAVTTRCAL supply current during device configuration. 5. Typical values are specified at nominal voltage, 25C.
GTP Transceiver DC Input and Output Levels
Table 16 summarizes the DC output specifications of the GTP transceivers in Spartan-6 FPGAs. Figure 1 shows the singleended output voltage swing. Figure 2 shows the peak-to-peak differential output voltage. Consult UG386: Spartan-6 FPGA GTP Transceivers User Guide for further details. Table 16: GTP Transceiver DC Specifications
Symbol
DVPPIN VIN VCMIN DVPPOUT VSEOUT VCMOUTDC RIN ROUT TOSKEW CEXT
DC Parameter
Differential peak-to-peak input voltage Absolute input voltage Common mode input voltage
Conditions
External AC coupled DC coupled MGTAVTTRX = 1.2V DC coupled MGTAVTTRX = 1.2V
Min
140 -400 - - -
Typ
- - 3/4 MGTAVTTRX - -
Max
2000 MGTAVTTRX - 1000 500
Units
mV mV mV mV mV mV ps nF
Differential peak-to-peak output Transmitter output swing is set voltage(1) to maximum setting Single-ended output voltage swing(1) Common mode output voltage Differential input resistance Differential output resistance Transmitter output skew Recommended external AC coupling capacitor(2) Equation based
MGTAVTTTX - VSEOUT/2 80 80 - 75 100 100 - 100 130 130 15 200
Notes: 1. The output swing and preemphasis levels are programmable using the attributes discussed in the Spartan-6 FPGA GTP Transceivers User Guide and can result in values lower than reported in this table. 2. Other values can be used as appropriate to conform to specific protocols and standards.
X-Ref Target - Figure 1
+V
P
Single-Ended Voltage
N 0
ds162_01_112009
Figure 1: Single-Ended Peak-to-Peak Voltage
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 2
+V
0
Differential Voltage
-V
P-N
ds162_02_112009
Figure 2: Differential Peak-to-Peak Voltage Table 17 summarizes the DC specifications of the clock input of the GTP transceiver. Consult the Spartan-6 FPGA GTP Transceivers User Guide for further details. Table 17: GTP Transceiver Clock DC Input Level Specification
Symbol
VIDIFF RIN CEXT
DC Parameter
Differential peak-to-peak input voltage Differential input resistance Required external AC coupling capacitor
Min
200 80 -
Typ
800 100 100
Max
2000 120 -
Units
mV nF
GTP Transceiver Switching Characteristics
Consult the Spartan-6 FPGA GTP Transceivers User Guide for further information. Table 18: GTP Transceiver Performance
Symbol
FGTPMAX FGTPRANGE1 FGTPRANGE2 FGTPRANGE3 FGPLLMAX FGPLLMIN
Description
Maximum GTP transceiver data rate GTP transceiver data rate range when PLL_TXDIVSEL_OUT = 1 GTP transceiver data rate range when PLL_TXDIVSEL_OUT = 2 GTP transceiver data rate range when PLL_TXDIVSEL_OUT = 4 Maximum PLL frequency Minimum PLL frequency
Speed Grade -4
3.2 1.88 to 3.2 0.94 to 1.62 0.6 to 0.81 1.62 0.94
-3
3.2 1.88 to 3.2 0.94 to 1.62 0.6 to 0.81 1.62 0.94
-2
2.7 1.88 to 2.7 0.94 to 1.62 0.6 to 0.81 1.62 0.94
-1L
N/A N/A N/A N/A N/A N/A
Units
Gb/s Gb/s Gb/s Gb/s GHz GHz
Table 19: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
FGTPDRPCLK
Description
GTP transceiver DCLK (DRP clock) maximum frequency
Speed Grade -4
160
-3
125
-2
100
-1L
N/A
Units
MHz
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 20: GTP Transceiver Reference Clock Switching Characteristics
Symbol
FGCLK TRCLK TFCLK TDCREF TLOCK TPHASE
Description
Reference clock frequency range Reference clock rise time Reference clock fall time Reference clock duty cycle Clock recovery frequency acquisition time 20% - 80% 80% - 20%
Conditions
All LXT Speed Grades Min
60 - - 45 - -
Typ
- 200 200 50 - -
Max
160 - - 55 1 200
Units
MHz ps ps % ms s
Transceiver PLL only Initial PLL lock
Clock recovery phase acquisition time Lock to data after PLL has locked to the reference clock
X-Ref Target - Figure 3
TRCLK
80%
20%
TFCLK
ds162_05_042109
Figure 3: Reference Clock Timing Parameters Table 21: GTP Transceiver User Clock Switching Characteristics(1)
Symbol
FTXOUT FRXREC TRX TRX2
Description
TXOUTCLK maximum frequency RXRECCLK maximum frequency RXUSRCLK maximum frequency RXUSRCLK2 maximum frequency
Conditions
Speed Grade -4
320 320 320
-3
320 320 320 156.25 160 80 320 156.25 160 80
-2
270 270 270 125 125 67.5 270 125 125 67.5
-1L
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
Units
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
1 byte interface 2 byte interface 4 byte interface
156.25 160 80 320 156.25 160 80
TTX TTX2
TXUSRCLK maximum frequency TXUSRCLK2 maximum frequency 1 byte interface 2 byte interface 4 byte interface
Notes: 1. Clocking must be implemented as described in the Spartan-6 FPGA GTP Transceivers User Guide.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 22: GTP Transceiver Transmitter Switching Characteristics
Symbol
TRTX TFTX TLLSKEW VTXOOBVDPP TTXOOBTRANSITION TJ3.125 DJ3.125 TJ2.5 DJ2.5 TJ1.62 DJ1.62 TJ1.25 DJ1.25 TJ614 DJ614 TX Rise time TX Fall time TX lane-to-lane skew(1) Electrical idle amplitude Electrical idle transition time Total Jitter(2) 3.125 Gb/s 2.5 Gb/s Jitter(2) 1.62 Gb/s 1.25 Gb/s Jitter(2) 614 Mb/s Deterministic Jitter(2) Total Jitter(2) Deterministic Total Jitter(2)
Description
Condition
20%-80% 80%-20%
Min
- - - - - - - - - - - - - - -
Typ
140 120 - - - - - - - - - - - - -
Max
- - 400 20 50 0.35 0.15 0.33 0.15 0.20 0.10 0.20 0.10 0.10 0.05
Units
ps ps ps mV ns UI UI UI UI UI UI UI UI UI UI
Deterministic Jitter(2) Total Jitter(2) Deterministic Total Jitter(2)
Deterministic Jitter(2)
Notes: 1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP transceiver sites. 2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
Table 23: GTP Transceiver Receiver Switching Characteristics
Symbol
TRXELECIDLE RXOOBVDPP RXSST RXRL
Description
Time for RXELECIDLE to respond to loss or restoration of data OOB detect threshold peak-to-peak Receiver spread-spectrum tracking(1) Run length (CID) CDR 2nd-order Modulated @ 33 KHz loop disabled Internal AC capacitor bypassed
Min
- 60 -5000 - -200
Typ
75 - - - - - - - - - - - - - - - -
Max
- 150 0 150 200 2000 2000 1000 - - - - - - - - -
Units
ns mV ppm UI ppm ppm ppm ppm UI UI UI UI UI UI UI UI UI
RXPPMTOL
Data/REFCLK PPM offset tolerance
PLL_RXDIVSEL_OUT = 1 -2000 CDR 2nd-order PLL_RXDIVSEL_OUT = 2 -2000 loop enabled PLL_RXDIVSEL_OUT = 4 -1000 3.125 Gb/s 2.5 Gb/s 1.62 Gb/s 1.25 Gb/s 614 Mb/s 3.125 Gb/s 3.125 Gb/s 2.7 Gb/s 2.7 Gb/s 0.4 0.4 0.5 0.5 0.5 0.65 0.1 0.65 0.1
SJ Jitter
Tolerance(2)
Sinusoidal Jitter(3) Sinusoidal Jitter(3) Sinusoidal Sinusoidal Sinusoidal Jitter(3) Jitter(3) Jitter(3)
JT_SJ3.125 JT_SJ2.5 JT_SJ1.62 JT_SJ1.25 JT_SJ614 JT_TJSE3.125 JT_SJSE3.125 JT_TJSE2.7 JT_SJSE2.7
SJ Jitter Tolerance with Stressed Eye(2)(5)
Total Jitter with stressed eye(4) Sinusoidal Jitter with stressed eye Total Jitter with stressed eye(4) Sinusoidal Jitter with stressed eye
Notes: 1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4. 2. All jitter values are based on a Bit Error Ratio of 1e-12. 3. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter. 4. Composed of 0.37 UI DJ in the form of ISI and 0.18 UI RJ. 5. Measured using PRBS7 data pattern.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Endpoint Block for PCI Express Designs Switching Characteristics
The Endpoint block for PCI Express is available in the Spartan-6 LXT family. Consult the Spartan-6 FPGA Integrated Endpoint Block for PCI Express for further information. Table 24: Maximum Performance for PCI Express Designs
Symbol
FPCIEUSER
Description
User clock maximum frequency
Speed Grade -4
62.5
-3
62.5
-2
62.5
-1L
N/A
Units
MHz
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Spartan-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the Switching Characteristics, page 17. Table 25: Interface Performances
Description
Networking Applications(1) SDR LVDS transmitter or receiver (using IOB SDR register) DDR LVDS transmitter or receiver (using IOB ODDR2/IDDR2 register) SDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8) DDR LVDS transmitter (using OSERDES2; DATA WIDTH = 2 to 8) SDR LVDS receiver (using ISERDES2; DATA WIDTH = 2 to 8) DDR LVDS receiver (using ISERDES2; DATA WIDTH = 2 to 8) 400 800 1080 1080 1080 1080 400 800 1050 1050 1050 1050 Block)(2) 400(4) 667(4) 667(4) 400(4) 800(4) 800(4) 375 750 950 950 950 950 Mb/s Mb/s Mb/s Mb/s Mb/s Mb/s
Speed Grade -4 -3 -2 -1L
Units
Memory Interfaces (Implemented using the Spartan-6 FPGA Memory Controller Standard Performance (standard VCCINT) DDR DDR2 DDR3 LPDDR (Mobile_DDR) Extended Performance (Requires Extended Memory Controller Block DDR2 DDR3
Notes:
400 667 667 400 VCCINT)(3) 800 800
400 625 625 400 --
Mb/s Mb/s Mb/s Mb/s
667 667
-- --
Mb/s Mb/s
1. 2. 3. 4.
Refer to XAPP1064, Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s). Refer to the Spartan-6 FPGA Memory Controller User Guide Extended Memory Controller block performance for DDR2 and DDR3 can be achieved using the extended MCB performance VCCINT range from Table 2. The -3N speed grade does not support a Memory Controller block.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Switching Characteristics
All values represented in this data sheet are based on these speed specifications: v1.11 for -4, -3, and -2; and v1.04 for -1L. Switching characteristics are specified on a per-speedgrade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Advance These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some underreporting might still occur. Preliminary These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Production These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. All specifications are always representative of worst-case supply voltage and junction temperature conditions. Since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. The -1L speed grade refers to the lower-power Spartan-6 devices. The -3N speed grade refers to the Spartan-6 devices that do not support MCB functionality. The -3N speed grade and -3 speed grade switching characteristics are identical. Table 26 correlates the current status of each Spartan-6 device on a per speed grade basis. Table 26: Spartan-6 Device Speed Grade Designations
Device
XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T Notes:
1. Until ISE software supports the -3N speed grade option, use the -3 speed grade option and do not use the Memory Controller block.
Speed Grade Designations Advance
-3, -2, -1L -3, -3N,-2, -1L -1L -1L -3, -3N, -2 -3, -3N, -2 -4, -3, -3N, -2 -1L -3, -3N, -2 -4, -3, -3N, -2 -1L -3, -3N, -2 -4, -3, -3N, -2 -1L -3, -3N, -2 -4, -3, -3N, -2 -1L -3, -3N, -2 -4, -3, -3N, -2
Preliminary
Production
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Spartan-6 devices.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Production Silicon and ISE Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases. Table 27 lists the production released Spartan-6 family member, speed grade, and the minimum corresponding supported speed specification version and ISE(R) software revisions. The ISE software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid. Table 27: Spartan-6 Device Production Software and Speed Specification Release(1)
Device
XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A ISE 12.2 v1.11(3) N/A
Speed Grade Designations(2) -4
N/A N/A N/A N/A ISE 12.1 v1.08 ISE 12.2 v1.11(3) ISE 12.2 v1.11(3) ISE 12.2 v1.11(3) ISE 12.1 v1.08 ISE 12.1 v1.08 ISE 12.2 v1.11(3) ISE 12.2 v1.11(3) ISE 12.2 v1.11(3) ISE 12.2 v1.11(3) ISE 12.2 v1.11(3) ISE 12.2 v1.11(3) ISE 12.2 v1.11(3) ISE 12.2 v1.11(3) N/A N/A N/A ISE 11.5 v1.07 ISE 12.1 v1.08 N/A N/A ISE 11.5 v1.06
-3
-3N
N/A
-2
-1L
Notes: 1. Blank entries indicate a device and/or speed grade in advance or preliminary status. 2. As marked with an N/A, LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade; LX4 devices are not available with a -3N speed grade. 3. ISE 12.2 software with v1.11 speed specification is available using ISE 12.2 software and the 12.2 Speed Files Patch available on the Xilinx Download Center.
IOB Pad Input/Output/3-State Switching Characteristics
Table 28 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIO input buffer. TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. Table 29 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state).
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 28: IOB Switching Characteristics
TIOPI I/O Standard -4
LVDS_33 LVDS_25 BLVDS_25 MINI_LVDS_33 MINI_LVDS_25 LVPECL_33 LVPECL_25 RSDS_33 (point to point) RSDS_25 (point to point) TMDS_33 PPDS_33 PPDS_25 PCI33_3 PCI66_3 DISPLAY_PORT I2C SMBUS SDIO MOBILE_DDR HSTL_I HSTL_II HSTL_III HSTL_I _18 HSTL_II _18 HSTL_III _18 SSTL3_I SSTL3_II SSTL2_I SSTL2_II SSTL18_I SSTL18_II SSTL15_II DIFF_HSTL_I DIFF_HSTL_II DIFF_HSTL_III DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 1.17 1.01 1.02 1.17 1.01 1.18 1.02 1.17 1.01 1.21 1.17 1.01 1.07 1.07 1.02 1.33 1.33 1.36 0.94 0.90 0.91 0.95 0.94 0.94 0.99 1.58 1.58 1.30 1.30 0.92 0.92 0.92 0.94 0.93 0.93 0.97 0.97 0.97
TIOOP Speed Grade -1L
1.50 1.39 1.39 1.50 1.39 1.50 1.39 1.50 1.38 1.53 1.50 1.38 1.39(1) 1.39(1) 1.38 1.64 1.64 1.66 1.25 1.21 1.22 1.26 1.25 1.25 1.29 1.98 1.98 1.69 1.70 1.23 1.23 1.23 1.28 1.27 1.28 1.32 1.31 1.32
TIOTP Speed Grade -1L
2.42 2.47 2.68 2.41 2.47 N/A N/A 2.42 2.47 2.50 2.43 2.47 4.38(1) 4.39(1) 4.08
Speed Grade -3
1.29 1.13 1.14 1.29 1.13 1.30 1.14 1.29 1.13 1.33 1.29 1.13 1.19 1.19 1.14 1.45 1.45 1.48 1.06 1.02 1.03 1.07 1.06 1.06 1.11 1.70 1.70 1.42 1.42 1.04 1.04 1.04 1.06 1.05 1.05 1.09 1.09 1.09
Units -1L
2.42 2.47 2.68 2.41 2.47 N/A N/A 2.42 2.47 2.50 2.43 2.47 4.38(1) 4.39(1) 4.08 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2
1.42 1.26 1.27 1.42 1.26 1.43 1.27 1.42 1.26 1.46 1.42 1.26 1.32 1.32 1.27 1.58 1.58 1.61 1.19 1.15 1.16 1.20 1.19 1.19 1.24 1.83 1.83 1.55 1.55 1.17 1.17 1.17 1.19 1.18 1.18 1.22 1.22 1.22
-4
1.55 1.65 1.72 1.57 1.65 N/A N/A 1.57 1.65 1.54 1.57 1.68 3.51 3.53 3.15
-3
1.69 1.79 1.86 1.71 1.79 N/A N/A 1.71 1.79 1.68 1.71 1.82 3.65 3.67 3.29
-2
1.89 1.99 2.06 1.91 1.99 N/A N/A 1.91 1.99 1.88 1.91 2.02 3.85 3.87 3.49
-4
1.55 1.65 1.72 1.57 1.65 N/A N/A 1.57 1.65 1.54 1.57 1.68 3.51 3.53 3.15
-3
1.69 1.79 1.86 1.71 1.79 N/A N/A 1.71 1.79 1.68 1.71 1.82 3.65 3.67 3.29
-2
1.89 1.99 2.06 1.91 1.99 N/A N/A 1.91 1.99 1.88 1.91 2.02 3.85 3.87 3.49
11.56 11.70 11.90 12.52 11.56 11.70 11.90 12.52 11.56 11.70 11.90 12.52 11.56 11.70 11.90 12.52 2.64 2.35 1.66 1.72 1.67 1.77 1.85 1.79 1.83 2.01 1.77 1.86 1.63 1.66 1.67 1.77 1.72 1.69 1.79 1.69 1.69 2.78 2.49 1.80 1.86 1.81 1.91 1.99 1.93 1.97 2.15 1.91 2.00 1.77 1.80 1.81 1.91 1.86 1.83 1.93 1.83 1.83 2.98 2.69 2.00 2.06 2.01 2.11 2.19 2.13 2.17 2.35 2.11 2.20 1.97 2.00 2.01 2.11 2.06 2.03 2.13 2.03 2.03 3.60 3.31 2.62 2.68 2.61 2.73 2.81 2.72 2.72 2.94 2.69 2.82 2.59 2.62 2.63 2.62 2.54 2.53 2.63 2.51 2.53 2.64 2.35 1.66 1.72 1.67 1.77 1.85 1.79 1.83 2.01 1.77 1.86 1.63 1.66 1.67 1.77 1.72 1.69 1.79 1.69 1.69 2.78 2.49 1.80 1.86 1.81 1.91 1.99 1.93 1.97 2.15 1.91 2.00 1.77 1.80 1.81 1.91 1.86 1.83 1.93 1.83 1.83 2.98 2.69 2.00 2.06 2.01 2.11 2.19 2.13 2.17 2.35 2.11 2.20 1.97 2.00 2.01 2.11 2.06 2.03 2.13 2.03 2.03 3.60 3.31 2.62 2.68 2.61 2.73 2.81 2.72 2.72 2.94 2.69 2.82 2.59 2.62 2.63 2.62 2.54 2.53 2.63 2.51 2.53
DS162 (v1.9) August 23, 2010 Advance Product Specification
www.xilinx.com 19
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 28: IOB Switching Characteristics (Cont'd)
TIOPI I/O Standard -4
DIFF_SSTL3_I DIFF_SSTL3_II DIFF_SSTL2_I DIFF_SSTL2_II DIFF_SSTL18_I DIFF_SSTL18_II DIFF_SSTL15_II DIFF_MOBILE_DDR LVTTL, QUIETIO, 2 mA LVTTL, QUIETIO, 4 mA LVTTL, QUIETIO, 6 mA LVTTL, QUIETIO, 8 mA LVTTL, QUIETIO, 12 mA LVTTL, QUIETIO, 16 mA LVTTL, QUIETIO, 24 mA LVTTL, Slow, 2 mA LVTTL, Slow, 4 mA LVTTL, Slow, 6 mA LVTTL, Slow, 8 mA LVTTL, Slow, 12 mA LVTTL, Slow, 16 mA LVTTL, Slow, 24 mA LVTTL, Fast, 2 mA LVTTL, Fast, 4 mA LVTTL, Fast, 6 mA LVTTL, Fast, 8 mA LVTTL, Fast, 12 mA LVTTL, Fast, 16 mA LVTTL, Fast, 24 mA LVCMOS33, QUIETIO, 2 mA LVCMOS33, QUIETIO, 4 mA LVCMOS33, QUIETIO, 6 mA LVCMOS33, QUIETIO, 8 mA LVCMOS33, QUIETIO, 12 mA LVCMOS33, QUIETIO, 16 mA LVCMOS33, QUIETIO, 24 mA LVCMOS33, Slow, 2 mA LVCMOS33, Slow, 4 mA 1.18 1.19 1.02 1.02 0.97 0.98 0.94 0.97 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.35 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34
TIOOP Speed Grade -1L
1.50 1.50 1.39 1.39 1.33 1.32 1.28 1.33 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64
TIOTP Speed Grade -1L
2.64 2.63 2.62 2.57 2.56 2.52 2.50 2.57 6.37 5.22 4.69 4.20 4.22 3.92 3.67 5.30 4.16 3.75 3.55 3.54 3.40 3.24 4.74 3.45 3.40 3.28 2.79 2.79 2.79 6.37 5.01 4.47 4.33 3.93 3.78 3.58 5.28 3.94
Speed Grade -3
1.30 1.31 1.14 1.14 1.09 1.10 1.06 1.09 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.47 1.46 1.46 1.46 1.46 1.46 1.46 1.46 1.46 1.46
Units -1L
2.64 2.63 2.62 2.57 2.56 2.52 2.50 2.57 6.37 5.22 4.69 4.20 4.22 3.92 3.67 5.30 4.16 3.75 3.55 3.54 3.40 3.24 4.74 3.45 3.40 3.28 2.79 2.79 2.79 6.37 5.01 4.47 4.33 3.93 3.78 3.58 5.28 3.94 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2
1.43 1.44 1.27 1.27 1.22 1.23 1.19 1.22 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.60 1.59 1.59 1.59 1.59 1.59 1.59 1.59 1.59 1.59
-4
1.81 1.80 1.80 1.76 1.72 1.68 1.67 1.75 5.39 4.29 3.75 3.23 3.28 2.94 2.69 4.36 3.17 2.76 2.59 2.58 2.39 2.28 3.78 2.49 2.44 2.32 1.83 1.83 1.83 5.40 4.03 3.51 3.37 2.94 2.77 2.59 4.37 2.98
-3
1.95 1.94 1.94 1.90 1.86 1.82 1.81 1.89 5.53 4.43 3.89 3.37 3.42 3.08 2.83 4.50 3.31 2.90 2.73 2.72 2.53 2.42 3.92 2.63 2.58 2.46 1.97 1.97 1.97 5.54 4.17 3.65 3.51 3.08 2.91 2.73 4.51 3.12
-2
2.15 2.14 2.14 2.10 2.06 2.02 2.01 2.09 5.73 4.63 4.09 3.57 3.62 3.28 3.03 4.70 3.51 3.10 2.93 2.92 2.73 2.62 4.12 2.83 2.78 2.66 2.17 2.17 2.17 5.74 4.37 3.85 3.71 3.28 3.11 2.93 4.71 3.32
-4
1.81 1.80 1.80 1.76 1.72 1.68 1.67 1.75 5.39 4.29 3.75 3.23 3.28 2.94 2.69 4.36 3.17 2.76 2.59 2.58 2.39 2.28 3.78 2.49 2.44 2.32 1.83 1.83 1.83 5.40 4.03 3.51 3.37 2.94 2.77 2.59 4.37 2.98
-3
1.95 1.94 1.94 1.90 1.86 1.82 1.81 1.89 5.53 4.43 3.89 3.37 3.42 3.08 2.83 4.50 3.31 2.90 2.73 2.72 2.53 2.42 3.92 2.63 2.58 2.46 1.97 1.97 1.97 5.54 4.17 3.65 3.51 3.08 2.91 2.73 4.51 3.12
-2
2.15 2.14 2.14 2.10 2.06 2.02 2.01 2.09 5.73 4.63 4.09 3.57 3.62 3.28 3.03 4.70 3.51 3.10 2.93 2.92 2.73 2.62 4.12 2.83 2.78 2.66 2.17 2.17 2.17 5.74 4.37 3.85 3.71 3.28 3.11 2.93 4.71 3.32
DS162 (v1.9) August 23, 2010 Advance Product Specification
www.xilinx.com 20
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 28: IOB Switching Characteristics (Cont'd)
TIOPI I/O Standard -4
LVCMOS33, Slow, 6 mA LVCMOS33, Slow, 8 mA LVCMOS33, Slow, 12 mA LVCMOS33, Slow, 16 mA LVCMOS33, Slow, 24 mA LVCMOS33, Fast, 2 mA LVCMOS33, Fast, 4 mA LVCMOS33, Fast, 6 mA LVCMOS33, Fast, 8 mA LVCMOS33, Fast, 12 mA LVCMOS33, Fast, 16 mA LVCMOS33, Fast, 24 mA LVCMOS25, QUIETIO, 2 mA LVCMOS25, QUIETIO, 4 mA LVCMOS25, QUIETIO, 6 mA LVCMOS25, QUIETIO, 8 mA LVCMOS25, QUIETIO, 12 mA LVCMOS25, QUIETIO, 16 mA LVCMOS25, QUIETIO, 24 mA LVCMOS25, Slow, 2 mA LVCMOS25, Slow, 4 mA LVCMOS25, Slow, 6 mA LVCMOS25, Slow, 8 mA LVCMOS25, Slow, 12 mA LVCMOS25, Slow, 16 mA LVCMOS25, Slow, 24 mA LVCMOS25, Fast, 2 mA LVCMOS25, Fast, 4 mA LVCMOS25, Fast, 6 mA LVCMOS25, Fast, 8 mA LVCMOS25, Fast, 12 mA LVCMOS25, Fast, 16 mA LVCMOS25, Fast, 24 mA LVCMOS18, QUIETIO, 2 mA LVCMOS18, QUIETIO, 4 mA LVCMOS18, QUIETIO, 6 mA LVCMOS18, QUIETIO, 8 mA LVCMOS18, QUIETIO, 12 mA 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34 1.34 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.82 1.18 1.18 1.18 1.18 1.18
TIOOP Speed Grade -1L
1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.64 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.13 1.86 1.86 1.86 1.86 1.86
TIOTP Speed Grade -1L
3.61 3.61 3.31 3.27 3.24 4.70 3.44 3.28 3.03 2.62 2.62 2.62 5.79 4.66 4.38 4.12 3.75 3.64 3.42 4.76 3.73 3.66 3.42 2.95 2.95 2.94 4.31 3.22 3.05 2.98 2.52 2.52 2.52 6.80 5.63 4.96 4.63 4.27
Speed Grade -3
1.46 1.46 1.46 1.46 1.46 1.46 1.46 1.46 1.46 1.46 1.46 1.46 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 1.30 1.30 1.30 1.30 1.30
Units -1L
3.61 3.61 3.31 3.27 3.24 4.70 3.44 3.28 3.03 2.62 2.62 2.62 5.79 4.66 4.38 4.12 3.75 3.64 3.42 4.76 3.73 3.66 3.42 2.95 2.95 2.94 4.31 3.22 3.05 2.98 2.52 2.52 2.52 6.80 5.63 4.96 4.63 4.27 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2
1.59 1.59 1.59 1.59 1.59 1.59 1.59 1.59 1.59 1.59 1.59 1.59 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.07 1.43 1.43 1.43 1.43 1.43
-4
2.58 2.65 2.39 2.31 2.28 3.76 2.48 2.32 2.07 1.65 1.65 1.65 4.81 3.70 3.46 3.20 2.83 2.64 2.45 3.78 2.79 2.73 2.48 2.01 2.01 2.01 3.35 2.25 2.09 2.02 1.56 1.56 1.56 5.92 4.74 4.05 3.71 3.35
-3
2.72 2.79 2.53 2.45 2.42 3.90 2.62 2.46 2.21 1.79 1.79 1.79 4.95 3.84 3.60 3.34 2.97 2.78 2.59 3.92 2.93 2.87 2.62 2.15 2.15 2.15 3.49 2.39 2.23 2.16 1.70 1.70 1.70 6.06 4.88 4.19 3.85 3.49
-2
2.92 2.99 2.73 2.65 2.62 4.10 2.82 2.66 2.41 1.99 1.99 1.99 5.15 4.04 3.80 3.54 3.17 2.98 2.79 4.12 3.13 3.07 2.82 2.35 2.35 2.35 3.69 2.59 2.43 2.36 1.90 1.90 1.90 6.26 5.08 4.39 4.05 3.69
-4
2.58 2.65 2.39 2.31 2.28 3.76 2.48 2.32 2.07 1.65 1.65 1.65 4.81 3.70 3.46 3.20 2.83 2.64 2.45 3.78 2.79 2.73 2.48 2.01 2.01 2.01 3.35 2.25 2.09 2.02 1.56 1.56 1.56 5.92 4.74 4.05 3.71 3.35
-3
2.72 2.79 2.53 2.45 2.42 3.90 2.62 2.46 2.21 1.79 1.79 1.79 4.95 3.84 3.60 3.34 2.97 2.78 2.59 3.92 2.93 2.87 2.62 2.15 2.15 2.15 3.49 2.39 2.23 2.16 1.70 1.70 1.70 6.06 4.88 4.19 3.85 3.49
-2
2.92 2.99 2.73 2.65 2.62 4.10 2.82 2.66 2.41 1.99 1.99 1.99 5.15 4.04 3.80 3.54 3.17 2.98 2.79 4.12 3.13 3.07 2.82 2.35 2.35 2.35 3.69 2.59 2.43 2.36 1.90 1.90 1.90 6.26 5.08 4.39 4.05 3.69
DS162 (v1.9) August 23, 2010 Advance Product Specification
www.xilinx.com 21
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 28: IOB Switching Characteristics (Cont'd)
TIOPI I/O Standard -4
LVCMOS18, QUIETIO, 16 mA LVCMOS18, QUIETIO, 24 mA LVCMOS18, Slow, 2 mA LVCMOS18, Slow, 4 mA LVCMOS18, Slow, 6 mA LVCMOS18, Slow, 8 mA LVCMOS18, Slow, 12 mA LVCMOS18, Slow, 16 mA LVCMOS18, Slow, 24 mA LVCMOS18, Fast, 2 mA LVCMOS18, Fast, 4 mA LVCMOS18, Fast, 6 mA LVCMOS18, Fast, 8 mA LVCMOS18, Fast, 12 mA LVCMOS18, Fast, 16 mA LVCMOS18, Fast, 24 mA LVCMOS18_JEDEC, QUIETIO, 2 mA LVCMOS18_JEDEC, QUIETIO, 4 mA LVCMOS18_JEDEC, QUIETIO, 6 mA LVCMOS18_JEDEC, QUIETIO, 8 mA 1.18 1.18 1.18 1.18 1.18 1.18 1.18 1.18 1.18 1.18 1.18 1.18 1.18 1.18 1.18 1.18 0.94 0.94 0.94 0.94
TIOOP Speed Grade -1L
1.86 1.86 1.86 1.86 1.86 1.86 1.86 1.86 1.86 1.86 1.86 1.86 1.86 1.86 1.86 1.86 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.61
TIOTP Speed Grade -1L
4.14 3.98 5.54 4.60 3.94 3.17 2.95 2.95 2.95 4.53 3.35 2.84 2.77 2.67 2.67 2.67 6.79 5.64 4.96 4.62 4.28 4.13 3.98 5.54 4.60 3.94 3.18 2.95 2.95 2.95 4.52 3.35 2.84 2.76 2.68 2.68 2.68 6.38
Speed Grade -3
1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.30 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.06 1.10
Units -1L
4.14 3.98 5.54 4.60 3.94 3.17 2.95 2.95 2.95 4.53 3.35 2.84 2.77 2.67 2.67 2.67 6.79 5.64 4.96 4.62 4.28 4.13 3.98 5.54 4.60 3.94 3.18 2.95 2.95 2.95 4.52 3.35 2.84 2.76 2.68 2.68 2.68 6.38 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2
1.43 1.43 1.43 1.43 1.43 1.43 1.43 1.43 1.43 1.43 1.43 1.43 1.43 1.43 1.43 1.43 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.19 1.23
-4
3.20 2.96 4.62 3.69 3.00 2.19 1.99 1.99 1.99 3.59 2.39 1.88 1.81 1.71 1.71 1.71 5.91 4.75 4.04 3.71 3.35 3.20 2.96 4.59 3.69 3.00 2.19 1.99 1.99 1.99 3.57 2.39 1.88 1.80 1.72 1.72 1.72 5.47
-3
3.34 3.10 4.76 3.83 3.14 2.33 2.13 2.13 2.13 3.73 2.53 2.02 1.95 1.85 1.85 1.85 6.05 4.89 4.18 3.85 3.49 3.34 3.10 4.73 3.83 3.14 2.33 2.13 2.13 2.13 3.71 2.53 2.02 1.94 1.86 1.86 1.86 5.61
-2
3.54 3.30 4.96 4.03 3.34 2.53 2.33 2.33 2.33 3.93 2.73 2.22 2.15 2.05 2.05 2.05 6.25 5.09 4.38 4.05 3.69 3.54 3.30 4.93 4.03 3.34 2.53 2.33 2.33 2.33 3.91 2.73 2.22 2.14 2.06 2.06 2.06 5.81
-4
3.20 2.96 4.62 3.69 3.00 2.19 1.99 1.99 1.99 3.59 2.39 1.88 1.81 1.71 1.71 1.71 5.91 4.75 4.04 3.71 3.35 3.20 2.96 4.59 3.69 3.00 2.19 1.99 1.99 1.99 3.57 2.39 1.88 1.80 1.72 1.72 1.72 5.47
-3
3.34 3.10 4.76 3.83 3.14 2.33 2.13 2.13 2.13 3.73 2.53 2.02 1.95 1.85 1.85 1.85 6.05 4.89 4.18 3.85 3.49 3.34 3.10 4.73 3.83 3.14 2.33 2.13 2.13 2.13 3.71 2.53 2.02 1.94 1.86 1.86 1.86 5.61
-2
3.54 3.30 4.96 4.03 3.34 2.53 2.33 2.33 2.33 3.93 2.73 2.22 2.15 2.05 2.05 2.05 6.25 5.09 4.38 4.05 3.69 3.54 3.30 4.93 4.03 3.34 2.53 2.33 2.33 2.33 3.91 2.73 2.22 2.14 2.06 2.06 2.06 5.81
LVCMOS18_JEDEC, QUIETIO, 12 mA 0.94 LVCMOS18_JEDEC, QUIETIO, 16 mA 0.94 LVCMOS18_JEDEC, QUIETIO, 24 mA 0.94 LVCMOS18_JEDEC, Slow, 2 mA LVCMOS18_JEDEC, Slow, 4 mA LVCMOS18_JEDEC, Slow, 6 mA LVCMOS18_JEDEC, Slow, 8 mA LVCMOS18_JEDEC, Slow, 12 mA LVCMOS18_JEDEC, Slow, 16 mA LVCMOS18_JEDEC, Slow, 24 mA LVCMOS18_JEDEC, Fast, 2 mA LVCMOS18_JEDEC, Fast, 4 mA LVCMOS18_JEDEC, Fast, 6 mA LVCMOS18_JEDEC, Fast, 8 mA LVCMOS18_JEDEC, Fast, 12 mA LVCMOS18_JEDEC, Fast, 16 mA LVCMOS18_JEDEC, Fast, 24 mA LVCMOS15, QUIETIO, 2 mA 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.94 0.98
DS162 (v1.9) August 23, 2010 Advance Product Specification
www.xilinx.com 22
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 28: IOB Switching Characteristics (Cont'd)
TIOPI I/O Standard -4
LVCMOS15, QUIETIO, 4 mA LVCMOS15, QUIETIO, 6 mA LVCMOS15, QUIETIO, 8 mA LVCMOS15, QUIETIO, 12 mA LVCMOS15, QUIETIO, 16 mA LVCMOS15, Slow, 2 mA LVCMOS15, Slow, 4 mA LVCMOS15, Slow, 6 mA LVCMOS15, Slow, 8 mA LVCMOS15, Slow, 12 mA LVCMOS15, Slow, 16 mA LVCMOS15, Fast, 2 mA LVCMOS15, Fast, 4 mA LVCMOS15, Fast, 6 mA LVCMOS15, Fast, 8 mA LVCMOS15, Fast, 12 mA LVCMOS15, Fast, 16 mA LVCMOS15_JEDEC, QUIETIO, 2 mA LVCMOS15_JEDEC, QUIETIO, 4 mA LVCMOS15_JEDEC, QUIETIO, 6 mA LVCMOS15_JEDEC, QUIETIO, 8 mA 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 0.98 1.03 1.03 1.03 1.03
TIOOP Speed Grade -1L
1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.61 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.31 1.33 1.33 1.33
TIOTP Speed Grade -1L
5.51 4.97 4.81 4.51 4.31 5.11 4.34 3.24 3.25 2.99 2.97 4.24 3.22 2.74 2.69 2.64 2.64 6.37 5.51 4.97 4.81 4.51 4.31 5.13 4.35 3.25 3.26 2.97 2.97 4.22 3.23 2.74 2.69 2.63 2.63 7.30 5.90 5.55
Speed Grade -3
1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.10 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.15 1.03 1.03 1.03
Units -1L
5.51 4.97 4.81 4.51 4.31 5.11 4.34 3.24 3.25 2.99 2.97 4.24 3.22 2.74 2.69 2.64 2.64 6.37 5.51 4.97 4.81 4.51 4.31 5.13 4.35 3.25 3.26 2.97 2.97 4.22 3.23 2.74 2.69 2.63 2.63 7.30 5.90 5.55 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2
1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.23 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.28 1.16 1.16 1.16
-4
4.61 4.07 3.91 3.53 3.32 4.18 3.42 2.29 2.30 2.03 2.01 3.29 2.27 1.78 1.73 1.73 1.73 5.49 4.61 4.07 3.92 3.54 3.33 4.18 3.42 2.29 2.30 2.01 2.01 3.28 2.27 1.78 1.73 1.73 1.73 6.40 4.98 4.65
-3
4.75 4.21 4.05 3.67 3.46 4.32 3.56 2.43 2.44 2.17 2.15 3.43 2.41 1.92 1.87 1.87 1.87 5.63 4.75 4.21 4.06 3.68 3.47 4.32 3.56 2.43 2.44 2.15 2.15 3.42 2.41 1.92 1.87 1.87 1.87 6.54 5.12 4.79
-2
4.95 4.41 4.25 3.87 3.66 4.52 3.76 2.63 2.64 2.37 2.35 3.63 2.61 2.12 2.07 2.07 2.07 5.83 4.95 4.41 4.26 3.88 3.67 4.52 3.76 2.63 2.64 2.35 2.35 3.62 2.61 2.12 2.07 2.07 2.07 6.74 5.32 4.99
-4
4.61 4.07 3.91 3.53 3.32 4.18 3.42 2.29 2.30 2.03 2.01 3.29 2.27 1.78 1.73 1.73 1.73 5.49 4.61 4.07 3.92 3.54 3.33 4.18 3.42 2.29 2.30 2.01 2.01 3.28 2.27 1.78 1.73 1.73 1.73 6.40 4.98 4.65
-3
4.75 4.21 4.05 3.67 3.46 4.32 3.56 2.43 2.44 2.17 2.15 3.43 2.41 1.92 1.87 1.87 1.87 5.63 4.75 4.21 4.06 3.68 3.47 4.32 3.56 2.43 2.44 2.15 2.15 3.42 2.41 1.92 1.87 1.87 1.87 6.54 5.12 4.79
-2
4.95 4.41 4.25 3.87 3.66 4.52 3.76 2.63 2.64 2.37 2.35 3.63 2.61 2.12 2.07 2.07 2.07 5.83 4.95 4.41 4.26 3.88 3.67 4.52 3.76 2.63 2.64 2.35 2.35 3.62 2.61 2.12 2.07 2.07 2.07 6.74 5.32 4.99
LVCMOS15_JEDEC, QUIETIO, 12 mA 1.03 LVCMOS15_JEDEC, QUIETIO, 16 mA 1.03 LVCMOS15_JEDEC, Slow, 2 mA LVCMOS15_JEDEC, Slow, 4 mA LVCMOS15_JEDEC, Slow, 6 mA LVCMOS15_JEDEC, Slow, 8 mA LVCMOS15_JEDEC, Slow, 12 mA LVCMOS15_JEDEC, Slow, 16 mA LVCMOS15_JEDEC, Fast, 2 mA LVCMOS15_JEDEC, Fast, 4 mA LVCMOS15_JEDEC, Fast, 6 mA LVCMOS15_JEDEC, Fast, 8 mA LVCMOS15_JEDEC, Fast, 12 mA LVCMOS15_JEDEC, Fast, 16 mA LVCMOS12, QUIETIO, 2 mA LVCMOS12, QUIETIO, 4 mA LVCMOS12, QUIETIO, 6 mA 1.03 1.03 1.03 1.03 1.03 1.03 1.03 1.03 1.03 1.03 1.03 1.03 0.91 0.91 0.91
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 28: IOB Switching Characteristics (Cont'd)
TIOPI I/O Standard -4
LVCMOS12, QUIETIO, 8 mA LVCMOS12, QUIETIO, 12 mA LVCMOS12, Slow, 2 mA LVCMOS12, Slow, 4 mA LVCMOS12, Slow, 6 mA LVCMOS12, Slow, 8 mA LVCMOS12, Slow, 12 mA LVCMOS12, Fast, 2 mA LVCMOS12, Fast, 4 mA LVCMOS12, Fast, 6 mA LVCMOS12, Fast, 8 mA LVCMOS12, Fast, 12 mA LVCMOS12_JEDEC, QUIETIO, 2 mA LVCMOS12_JEDEC, QUIETIO, 4 mA LVCMOS12_JEDEC, QUIETIO, 6 mA LVCMOS12_JEDEC, QUIETIO, 8 mA 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 0.91 1.50 1.50 1.50 1.50
TIOOP Speed Grade -1L
1.33 1.33 1.33 1.33 1.33 1.33 1.33 1.33 1.33 1.33 1.33 1.33 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70 1.70
TIOTP Speed Grade -1L
5.21 4.94 5.91 3.81 3.72 3.31 3.06 4.44 3.30 2.75 2.64 2.62 7.31 5.88 5.54 5.22 4.94 5.90 3.80 3.72 3.30 3.05 4.42 3.31 2.76 2.65 2.62
Speed Grade -3
1.03 1.03 1.03 1.03 1.03 1.03 1.03 1.03 1.03 1.03 1.03 1.03 1.62 1.62 1.62 1.62 1.62 1.62 1.62 1.62 1.62 1.62 1.62 1.62 1.62 1.62 1.62
Units -1L
5.21 4.94 5.91 3.81 3.72 3.31 3.06 4.44 3.30 2.75 2.64 2.62 7.31 5.88 5.54 5.22 4.94 5.90 3.80 3.72 3.30 3.05 4.42 3.31 2.76 2.65 2.62 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-2
1.16 1.16 1.16 1.16 1.16 1.16 1.16 1.16 1.16 1.16 1.16 1.16 1.75 1.75 1.75 1.75 1.75 1.75 1.75 1.75 1.75 1.75 1.75 1.75 1.75 1.75 1.75
-4
4.23 3.98 4.98 2.84 2.77 2.34 2.08 3.46 2.35 1.79 1.68 1.66 6.39 4.98 4.67 4.23 3.99 5.00 2.85 2.76 2.35 2.09 3.46 2.35 1.79 1.69 1.66
-3
4.37 4.12 5.12 2.98 2.91 2.48 2.22 3.60 2.49 1.93 1.82 1.80 6.53 5.12 4.81 4.37 4.13 5.14 2.99 2.90 2.49 2.23 3.60 2.49 1.93 1.83 1.80
-2
4.57 4.32 5.32 3.18 3.11 2.68 2.42 3.80 2.69 2.13 2.02 2.00 6.73 5.32 5.01 4.57 4.33 5.34 3.19 3.10 2.69 2.43 3.80 2.69 2.13 2.03 2.00
-4
4.23 3.98 4.98 2.84 2.77 2.34 2.08 3.46 2.35 1.79 1.68 1.66 6.39 4.98 4.67 4.23 3.99 5.00 2.85 2.76 2.35 2.09 3.46 2.35 1.79 1.69 1.66
-3
4.37 4.12 5.12 2.98 2.91 2.48 2.22 3.60 2.49 1.93 1.82 1.80 6.53 5.12 4.81 4.37 4.13 5.14 2.99 2.90 2.49 2.23 3.60 2.49 1.93 1.83 1.80
-2
4.57 4.32 5.32 3.18 3.11 2.68 2.42 3.80 2.69 2.13 2.02 2.00 6.73 5.32 5.01 4.57 4.33 5.34 3.19 3.10 2.69 2.43 3.80 2.69 2.13 2.03 2.00
LVCMOS12_JEDEC, QUIETIO, 12 mA 1.50 LVCMOS12_JEDEC, Slow, 2 mA LVCMOS12_JEDEC, Slow, 4 mA LVCMOS12_JEDEC, Slow, 6 mA LVCMOS12_JEDEC, Slow, 8 mA LVCMOS12_JEDEC, Slow, 12 mA LVCMOS12_JEDEC, Fast, 2 mA LVCMOS12_JEDEC, Fast, 4 mA LVCMOS12_JEDEC, Fast, 6 mA LVCMOS12_JEDEC, Fast, 8 mA LVCMOS12_JEDEC, Fast, 12 mA Notes:
1.
1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50 1.50
Devices with a -1L speed grade do not support Xilinx PCI IP.
Table 29: IOB 3-state ON Output Switching Characteristics (TIOTPHZ)
Symbol
TIOTPHZ
Description
T input to Pad high-impedance
Speed Grade -4
1.39
-3
1.59
-2
1.59
-1L
1.91
Units
ns
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 30 shows the test setup parameters used for measuring input delay. Table 30: Input Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V LVCMOS, 1.2V PCI (Peripheral Component Interface), 33 MHz and 66 MHz, 3.3V HSTL (High-Speed Transceiver Logic), Class I & II HSTL, Class III HSTL, Class I & II, 1.8V HSTL, Class III 1.8V SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3V SSTL, Class I & II, 2.5V SSTL, Class I & II, 1.8V SSTL, Class II, 1.5V LVDS (Low-Voltage Differential Signaling), 2.5V & 3.3V LVPECL (Low-Voltage Positive Emitter-Coupled Logic), 2.5V & 3.3V BLVDS (Bus LVDS), 2.5V Mini-LVDS, 2.5V & 3.3V RSDS (Reduced Swing Differential Signaling), 2.5V & 3.3V TMDS (Transition Minimized Differential Signaling), 3.3V PPDS (Point-to-Point Differential Signaling, 2.5V & 3.3V I/O Standard Attribute LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3, PCI66_3 HSTL_I, HSTL_II HSTL_III HSTL_I_18, HSTL_II_18 HSTL_III_18 SSTL3_I, SSTL3_II SSTL2_I, SSTL2_II SSTL18_I, SSTL18_II SSTL15_II LVDS_25, LVDS_33 LVPECL_25, LVPECL_33 BLVDS_25 MINI_LVDS_25, MINI_LVDS_33 RSDS_25, RSDS_33 TMDS_33 PPDS_25, PPDS_33
VL(1)
0 0 0 0 0 0
VH(1)
3.0 3.3 2.5 1.8 1.5 1.2
VMEAS(3)(4) VREF(2)(4)
1.4 1.65 1.25 0.9 0.75 0.6 - - - - - - - VREF VREF VREF VREF VREF VREF VREF VREF 0(5) 0(5) 0(5) 0(5) 0(5) 0(5) 0(5) 0.75 0.90 0.90 1.1 1.5 1.25 0.90 0.75 - - - - - - -
Per PCI Specification VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.5 VREF - 0.75 VREF - 0.75 VREF - 0.5 VREF - 0.2 1.25 - 0.125 1.2 - 0.3 1.3 - 0.125 1.2 - 0.125 1.2 - 0.1 3.0 - 0.1 1.25 - 0.1 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.5 VREF + 0.75 VREF + 0.75 VREF + 0.5 VREF + 0.2 1.25 + 0.125 1.2 - 0.3 1.3 + 0.125 1.2 + 0.125 1.2 + 0.1 3.0 + 0.1 1.25 + 0.1
Notes: 1. Input waveform switches between VL and VH. 2. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical. 3. Input voltage level from which measurement starts. 4. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 4. 5. The value given is the differential input voltage.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
Output delays are measured using a Tektronix P6245 TDS500/600 probe (< 1 pF) across approximately 4" of FR4 microstrip trace. Standard termination was used for all testing. The propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in Figure 4 and Figure 5.
X-Ref Target - Figure 4
X-Ref Target - Figure 5
FPGA Output
+ CREF RREF VMEAS -
ds162_07_011309
VREF
Figure 5: Differential Test Setup Measurements and test conditions are reflected in the IBIS models except where the IBIS format precludes it. Parameters VREF , RREF , CREF , and VMEAS fully describe the test conditions for each I/O standard. The most accurate prediction of propagation delay in any given application can be obtained through IBIS simulation, using the following method: 1. Simulate the output driver of choice into the generalized test setup, using values from Table 31. 2. Record the time to VMEAS .
ds162_06_011309
FPGA Output
RREF
VMEAS
(voltage level when taking delay measurement)
CREF
(probe capacitance)
Figure 4: Single-Ended Test Setup
3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load. 4. Record the time to VMEAS . 5. Compare the results of steps 2 and 4. The increase or decrease in delay yields the actual propagation delay of the PCB trace.
Table 31: Output Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic) LVCMOS (Low-Voltage CMOS), 3.3V LVCMOS, 2.5V LVCMOS, 1.8V LVCMOS, 1.5V LVCMOS, 1.2V PCI (Peripheral Component Interface) 33 MHz and 66 MHz, 3.3V HSTL (High-Speed Transceiver Logic), Class I HSTL, Class II HSTL, Class III HSTL, Class I, 1.8V HSTL, Class II, 1.8V HSTL, Class III, 1.8V SSTL (Stub Series Terminated Logic), Class I, 1.8V SSTL, Class II, 1.8V SSTL, Class I, 2.5V
I/O Standard Attribute
LVTTL (all) LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3, PCI66_3 (rising edge) PCI33_3, PCI66_3 (falling edge) HSTL_I HSTL_II HSTL_III HSTL_I_18 HSTL_II_18 HSTL_III_18 SSTL18_I SSTL18_II SSTL2_I
RREF ()
1M 1M 1M 1M 1M 1M 25 25 50 25 50 50 25 50 50 25 50
CREF(1) (pF)
0 0 0 0 0 0 10 (2) 10 (2) 0 0 0 0 0 0 0 0 0
VMEAS (V)
1.4 1.65 1.25 0.9 0.75 0.75 0.94 2.03 VREF VREF 0.9 VREF VREF 1.1 VREF VREF VREF
VREF (V)
0 0 0 0 0 0 0 3.3 0.75 0.75 1.5 0.9 0.9 1.8 0.9 0.9 1.25
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 31: Output Delay Measurement Methodology (Cont'd)
Description
SSTL, Class II, 2.5V SSTL, Class II, 1.5V LVDS (Low-Voltage Differential Signaling), 2.5V & 3.3V BLVDS (Bus LVDS), 2.5V Mini-LVDS, 2.5V & 3.3V SSTL2_II SSTL15_II LVDS_25, LVDS_33 BLVDS_25 MINI_LVDS_25, MINI_LVDS_33
I/O Standard Attribute
RREF ()
25 25 100 100 100 100 100 100
CREF(1) (pF)
0 0 0 0 0 0 0 0
VMEAS (V)
VREF VREF 0(3) 0(3) 0(3) 0(3) 0(3) 0(3)
VREF (V)
1.25 0.75 1.2 0 1.2 1.2
RSDS (Reduced Swing Differential Signaling), 2.5V & 3.3V RSDS_25, RSDS_33 TMDS (Transition Minimized Differential Signaling), 3.3V PPDS (Point-to-Point Differential Signaling, 2.5V & 3.3V
Notes: 1. CREF is the capacitance of the probe, nominally 0 pF. 2. Per PCI specifications. 3. The value given is the differential output voltage.
TMDS_33 PPDS_25, PPDS_33
-
Simultaneously Switching Outputs
Due to lead inductance, a given package supports a limited number of simultaneous switching outputs (SSOs) when using fast, high-drive outputs. Table 32 and Table 33 provide guidelines for the recommended maximum allowable number of SSOs. These guidelines describe the maximum number of user I/O pins of an output signal standard that should simultaneously switch in the same direction, while maintaining a safe level of switching noise for that particular signal standard. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of GND and power bounce. For each device/package combination, Table 32 provides the number of equivalent VCCO/GND pairs per bank. For each output signal standard and drive strength, Table 33 recommends the maximum number of SSOs, switching in the same direction, allowed per VCCO/GND pair within an I/O bank. The guidelines are categorized by package style, slew rate, and output drive current. The number of SSOs are also specified by I/O bank. Multiply the appropriate numbers from each table to calculate the maximum number of SSOs allowed within an I/O bank. The guidelines assume that all pins within a bank use the same I/O standard. Exceeding these SSO guidelines can result in increased power or GND bounce, degraded signal integrity, or increased system jitter. For a given I/O standard, if the SSO limit per pair in Table 33 is greater than the maximum I/O per pair in Table 32, then there is no SSO limit for the exclusive use of that I/O standard. The recommended maximum SSO values assume that the FPGA is soldered on a printed circuit board and that the board uses sound design practices. Due to the additional lead inductance introduced by the socket, the SSO values do not apply for FPGAs mounted in sockets. The SSO values assume that the VCCAUX is powered at 3.3V. Setting VCCAUX to 2.5V provides better SSO characteristics. For more detail, see the Spartan-6 FPGA SelectIO Resources User Guide.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 32: Spartan-6 FPGA VCCO/GND Pairs per Bank
Package
TQG144 LX
Devices
Description
VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair VCCO/GND Pairs Maximum I/O per Pair
Bank 0
3 8 4 6 4 10 5 8 6 10 4 4 8 7 7 5 10 6 6 7 12 3 12 9 10 8 17 7 15 7
Bank 1
3 8 6 4 4 10 6 9 6 9 6 9 13 8 12 8 10 8 10 8 15 7 9 10 8 7 14 6 14 6
Bank 2
2 13 4 7 4 9 4 9 6 10 6 10 8 7 8 6 11 9 11 7 10 8 10 9 10 8 17 7 13 8
Bank 3
3 8 6 4 4 10 5 10 6 9 6 9 13 8 13 8 11 8 10 8 16 7 10 9 8 8 14 8 14 8
Bank 4
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 6 8 7 7 7 7 7 7
Bank 5
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 6 9 7 7 8 6 8 6
CPG196
LX
CSG225
LX
FT(G)256
LX
LX CSG324 LXT
LX CSG484 LXT
LX FG(G)484 LXT
LX45
FG(G)676
LX75, LX100, LX150
LXT
LX FG(G)900 LXT
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 33: SSO Limit per VCCO/GND Pair
SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 Bank 0/2
Fast 2 Slow QuietIO Fast 4 Slow QuietIO Fast 1.2V LVCMOS12, LVCMOS12_JEDEC 6 Slow QuietIO Fast 8 Slow QuietIO Fast 12 Slow QuietIO 30 (1) 51 71 17 23 35 13 19 26 N/A N/A N/A N/A N/A N/A
All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2
30 51 71 17 23 35 13 19 26 N/A N/A N/A N/A N/A N/A
Bank 1/3
35 55 58 17 25 32 15 20 24 12 15 20 5 8 11
Bank 1/3/4/5
35 52 70 19 22 32 14 17 24 12 13 19 4 5 10
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont'd)
SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 Bank 0/2
Fast 2 Slow QuietIO Fast 4 Slow QuietIO Fast 6 LVCMOS15, LVCMOS15_JEDEC 8 Slow QuietIO Fast Slow QuietIO 1.5V Fast 12 Slow QuietIO Fast 16 HSTL_I HSTL_II HSTL_III DIFF_HSTL_I DIFF_HSTL_II DIFF_HSTL_III SSTL_15_II
(3) (3)
All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2
33 57 70 19 30 38 14 18 27 11 16 23 N/A N/A N/A N/A N/A N/A 9 N/A 7 27 N/A 21 N/A N/A
Bank 1/3
40 62 67 21 30 33 16 19 24 13 16 20 5 8 10 5 8 10 10 5 9 30 15 27 5 15
Bank 1/3/4/5
41 56 66 21 24 30 16 17 21 12 14 17 4 5 9 4 8 9 10 6 9 30 18 27 4 12
33 57 70 19 30 38 14 18 27 11 16 23 N/A N/A N/A N/A N/A N/A 9 N/A 7 27 N/A 21 N/A N/A
Slow QuietIO
DIFF_SSTL_15_II
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont'd)
SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 Bank 0/2
Fast 2 Slow QuietIO Fast 4 Slow QuietIO Fast 6 Slow QuietIO Fast LVCMOS18, LVCMOS18_JEDEC 8 Slow QuietIO Fast 12 Slow QuietIO Fast 1.8V 16 Slow QuietIO Fast 24 HSTL_I_18 HSTL_II_18 HSTL_III_18 DIFF_HSTL_I_18 DIFF_HSTL_II_18 DIFF_HSTL_III_18 MOBILE_DDR (3) DIFF_MOBILE_DDR SSTL_18_I
(3) (3)
All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2
39 65 80 22 38 45 16 27 30 13 16 25 5 7 11 4 7 11 N/A N/A N/A 9 N/A 9 27 N/A 27 12 36 9 N/A 27 N/A
Bank 1/3
46 75 80 25 36 40 18 25 28 15 18 22 7 8 10 5 8 10 5 8 10 10 5 10 30 15 30 14 42 10 5 30 15
Bank 1/3/4/5
47 74 85 25 29 35 17 19 23 14 16 18 5 6 8 4 5 8 3 8 8 9 6 11 27 18 33 14 42 10 4 30 12
39 65 80 22 38 45 16 27 30 13 16 25 5 7 11 4 7 11 N/A N/A N/A 9 N/A 9 27 N/A 27 12 36 9 N/A
Slow QuietIO
SSTL_18_II (3) DIFF_SSTL_18_I DIFF_SSTL_18_II
(3) (3)
27 N/A
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont'd)
SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 Bank 0/2
Fast 2 Slow QuietIO Fast 4 Slow QuietIO Fast 6 Slow QuietIO Fast LVCMOS25 2.5V 12 8 Slow QuietIO Fast Slow QuietIO Fast 16 Slow QuietIO Fast 24 SSTL_2_I
(3)
All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2
38 46 57 21 26 33 15 19 25 12 15 21 1 2 3 1 3 4 N/A N/A N/A 10 N/A 30 N/A
Bank 1/3
43 52 64 24 31 32 17 22 23 15 18 19 3 7 8 3 7 9 3 5 8 11 7 33 21
Bank 1/3/4/5
43 48 59 23 27 30 16 19 19 14 16 16 1 4 8 1 3 8 1 2 6 11 7 33 24
38 46 57 21 26 33 15 19 25 12 15 21 1 2 3 1 3 4 N/A N/A N/A 10 N/A
Slow QuietIO
SSTL_2_II (3) DIFF_SSTL_2_I DIFF_SSTL_2_II
(3) (3)
30 N/A
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont'd)
SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 Bank 0/2
Fast 2 Slow QuietIO Fast 4 Slow QuietIO Fast 6 Slow QuietIO Fast 3.3V LVCMOS33 8 Slow QuietIO Fast 12 Slow QuietIO Fast 16 Slow QuietIO Fast 24 Slow QuietIO 42 50 60 21 32 39 14 19 29 11 15 25 1 2 4 1 1 3 1 2 7
All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2
42 50 60 21 32 39 14 19 29 11 15 25 1 2 4 1 1 3 1 2 7
Bank 1/3
46 55 68 27 37 42 19 25 30 15 20 24 3 5 9 2 5 10 2 5 9
Bank 1/3/4/5
44 49 60 25 32 37 17 22 25 14 18 20 1 2 7 1 1 8 1 1 7
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont'd)
SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 Bank 0/2
Fast 2 Slow QuietIO Fast 4 Slow QuietIO Fast 6 Slow QuietIO Fast LVTTL 8 Slow QuietIO Fast 3.3V 12 Slow QuietIO Fast 16 Slow QuietIO Fast 24 PCI33_3 PCI66_3 SSTL_3_I SSTL_3_II DIFF_SSTL_3_I DIFF_SSTL_3_II SDIO Slow QuietIO 53 70 79 23 34 44 16 21 34 12 16 27 1 2 2 1 1 3 1 2 8 18 18 5 3 15 9 17
All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2
53 70 79 23 34 44 16 21 34 12 16 27 1 2 2 1 1 3 1 2 8 18 18 5 3 15 9 17
Bank 1/3
65 80 89 30 41 49 21 28 39 16 22 28 3 5 10 3 7 11 2 5 9 19 19 8 5 24 15 18
Bank 1/3/4/5
62 73 91 27 37 46 20 25 34 15 19 24 1 4 8 1 2 8 1 2 8 19 19 8 3 24 9 15
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 33: SSO Limit per VCCO/GND Pair (Cont'd)
SSO Limit per VCCO/GND Pair VCCO I/O Standard Drive Slew All TQG144, CPG196, CSG225, FT(G)256, and LX devices in CSG324 Bank 0/2
LVDS_33 LVDS_25 BLVDS_25 MINI_LVDS_33 MINI_LVDS_25 RSDS_33 Various RSDS_25 TMDS_33 PPDS_33 PPDS_25 DISPLAY_PORT I2C SMBUS Notes:
1. 2. 3. SSO limits greater than the number of I/O per VCCO/GND pair (Table 32) indicate No Limit for the given I/O standard. They are provided in this table to calculate limits when using multiple I/O standards in a bank. Not available (N/A) indicates that the I/O standard is not available in the given bank. When used with the MCB, these signals are exempt from SSO analysis due to the known activity of the MCB switching patterns. SSO performance is validated for all MCB instances. MCB outputs can, in some cases, exceed the SSO limits.
All CSG484, FG(G)484, FG(G)676, FG(G)900, and LXT devices in CSG324 Bank 0/2
16 20 20 13 18 12 15 83 12 16 42 47 44
Bank 1/3
N/A N/A 48 N/A N/A N/A N/A N/A N/A N/A 40 55 52
Bank 1/3/4/5
N/A N/A 20 N/A N/A N/A N/A N/A N/A N/A 30 42 40
16 20 20 13 18 12 15 83 12 16 42 47 44
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Logic Switching Characteristics
Table 34: ILOGIC2 Switching Characteristics
Symbol
Setup/Hold TICE0CK/TICKCE0 TISRCK/TICKSR TIDOCK/TIOCKD TIDOCKD/TIOCKDD Combinatorial TIDI TIDID Sequential Delays TIDLO TIDLOD TICKQ TRQ_ILOGIC2 D pin to Q pin using flip-flop as a latch without Delay DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY2) CLK to Q outputs SR pin to Q outputs 1.56 0.68 1.03 1.81 1.86 0.97 1.24 1.81 2.39 1.20 1.43 2.50 3.22 1.89 1.66 3.05 ns ns ns ns D pin to O pin propagation delay, no Delay DDLY pin to O pin propagation delay (using IODELAY2) 0.95 0.23 1.28 0.39 1.53 0.44 1.97 0.64 ns ns CE0 pin Setup/Hold with respect to CLK SR pin Setup/Hold with respect to CLK D pin Setup/Hold with respect to CLK without Delay DDLY pin Setup/Hold with respect to CLK (using IODELAY2) 0.56 -0.30 0.74 -0.23 1.19 -0.83 0.31 0.00 0.56 -0.25 0.74 -0.22 1.36 -0.83 0.47 0.00 0.79 -0.22 0.98 -0.20 1.73 -0.83 0.54 0.00 1.24 -0.55 1.35 -0.49 1.97 -1.09 0.64 -0.16 ns ns ns ns
Description
Speed Grade -4 -3 -2 -1L
Units
Table 35: OLOGIC2 Switching Characteristics
Symbol
Setup/Hold TODCK/TOCKD TOOCECK/TOCKOCE TOSRCK/TOCKSR TOTCK/TOCKT TOTCECK/TOCKTCE Sequential Delays TOCKQ TRQ_OLOGIC2 CLK to OQ/TQ out SR pin to OQ/TQ out 0.55 1.81 0.51 1.81 0.74 2.50 0.97 3.05 ns ns D1/D2 pins Setup/Hold with respect to CLK OCE pin Setup/Hold with respect to CLK SR pin Setup/Hold with respect to CLK T1/T2 pins Setup/Hold with respect to CLK TCE pin Setup/Hold with respect to CLK 0.60 -0.05 0.75 -0.10 0.68 -0.28 0.24 -0.08 0.58 -0.06 0.86 -0.05 0.75 -0.10 0.79 -0.28 0.56 -0.06 0.72 -0.06 1.18 0.00 1.01 -0.05 1.03 -0.23 0.83 -0.01 1.18 -0.01 1.15 -0.26 0.56 -0.22 1.09 -0.46 0.86 -0.18 0.47 -0.12 ns ns ns ns ns
Description
Speed Grade -4 -3 -2 -1L
Units
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 36: ISERDES2 Switching Characteristics
Symbol
Setup/Hold for Control Lines TISCCK_BITSLIP/ TISCKC_BITSLIP TISCCK_CE / TISCKC_CE Setup/Hold for Data Lines TISDCK_D /TISCKD_D TISDCK_DDLY /TISCKD_DDLY TISDCK_D_DDR /TISCKD_D_DDR TISDCK_DDLY_DDR/ TISCKD_DDLY_DDR Sequential Delays TISCKO_Q CLKDIV to out at Q pin 1.30 1.44 2.02 2.22 ns D pin Setup/Hold with respect to CLK DDLY pin Setup/Hold with respect to CLK (using IODELAY2) D pin Setup/Hold with respect to CLK at DDR mode D pin Setup/Hold with respect to CLK at DDR mode (using IODELAY2) 0.24 -0.15 -0.25 0.30 -0.03 0.04 -0.40 0.48 0.25 -0.05 -0.25 0.42 -0.03 0.16 -0.40 0.53 0.29 -0.05 -0.25 0.56 -0.03 0.18 -0.40 0.71 0.12 -0.06 -0.54 0.67 -0.05 0.12 -0.71 0.86 ns ns ns ns BITSLIP pin Setup/Hold with respect to CLKDIV CE pin Setup/Hold with respect to CLK 0.16 -0.09 0.71 -0.47 0.20 -0.09 0.71 -0.42 0.31 -0.09 0.97 -0.42 0.34 -0.14 1.39 -0.71 ns ns
Description
Speed Grade -4 -3 -2 -1L
Units
Output Serializer/Deserializer Switching Characteristics
Table 37: OSERDES2 Switching Characteristics
Symbol
Setup/Hold TOSDCK_D/TOSCKD_D TOSDCK_T/TOSCKD_T(1) TOSCCK_OCE/TOSCKC_OCE TOSCCK_TCE/TOSCKC_TCE Sequential Delays TOSCKO_OQ TOSCKO_TQ Clock to out from CLK to OQ Clock to out from CLK to TQ 0.94 0.94 1.11 1.11 1.51 1.51 1.89 1.91 ns ns D input Setup/Hold with respect to CLKDIV T input Setup/Hold with respect to CLK OCE input Setup/Hold with respect to CLK TCE input Setup/Hold with respect to CLK -0.03 1.02 -0.05 1.03 0.12 -0.03 0.14 -0.08 -0.03 1.17 -0.05 1.13 0.15 -0.03 0.17 -0.08 -0.03 1.27 -0.05 1.23 0.24 -0.03 0.27 -0.08 -0.02 0.23 -0.05 0.24 0.28 -0.17 0.31 -0.16 ns ns ns ns
Description
Speed Grade -4 -3 -2 -1L
Units
Notes: 1. TOSDCK_T2/TOSCKD_T2 (T input setup/hold with respect to CLKDIV) are reported as TOSDCK_T/TOSCKD_T in TRACE report.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Delay Switching Characteristics
Table 38: IODELAY2 Switching Characteristics
Symbol
TIODCCK_CAL / TIODCKC_CAL TIODCCK_CE / TIODCKC_CE TIODCCK_INC/ TIODCKC_INC TIODCCK_RST/ TIODCKC_RST TTAP1(2) TTAP2 TTAP3 TTAP4 TTAP5 TTAP6 TTAP7 TTAP8 FMINCAL
Description
CAL pin Setup/Hold with respect to CK CE pin Setup/Hold with respect to CK INC pin Setup/Hold with respect to CK RST pin Setup/Hold with respect to CK Maximum tap 1 delay Maximum tap 2 delay Maximum tap 3 delay Maximum tap 4 delay Maximum tap 5 delay Maximum tap 6 delay Maximum tap 7 delay Maximum tap 8 delay Minimum allowed bit rate for calibration in variable mode: VARIABLE_FROM_ZERO, VARIABLE_FROM_HALF_MAX, and DIFF_PHASE_DETECTOR. Propagation delay through IODELAY2 Propagation delay through IODELAY2
Speed Grade -4
0.28 -0.13 0.14 -0.03 0.10 0.02 0.12 -0.02 8 40 95 108 171 207 212 292 188
-3
0.33 -0.13 0.17 -0.03 0.12 0.03 0.15 -0.02 14 66 120 141 194 249 276 341 188
-2
0.48 -0.13 0.25 -0.02 0.18 0.06 0.22 -0.01 16 77 140 166 231 292 343 424 188
-1L
0.57 -0.24 0.33 0.01 0.23 0.11 0.28 0.02
Units
ns ns ns ns ps ps ps ps ps ps ps ps Mb/s
TIODDO_IDATAIN TIODDO_ODATAIN
Note 1 Note 1
Note 1 Note 1
Note 1 Note 1
Note 1 Note 1
Notes: 1. Delay depends on IODELAY2 tap setting. See TRACE report for actual values. 2. Maximum delay = integer (number of taps/8) x TTAP8 + TTAPn (where n equals the remainder). For minimum delay consult the TRACE setup and hold report. Minimum delay is greater than 30% of the maximum delay.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
CLB Switching Characteristics (SLICEM Only)
Table 39: CLB Switching Characteristics (SLICEM Only)
Symbol
Combinatorial Delays TILO An - Dn LUT inputs to A to D outputs An - Dn LUT inputs through F7AMUX/F7BMUX to AMUX/CMUX output TOPAB TITO TTITO_LOGIC TOPCYA TOPCYB TOPCYC TOPCYD TAXCY TBXCY TCXCY TDXCY TBYP TCINA TCINB TCINC TCIND Sequential Delays TCKO TDICK/TCKDI TCECK/TCKCE TSRCK/TCKSR TCINCK/TCKCIN Set/Reset TRPW TRQ TCEO FTOG SR input minimum pulse width Delay from SR input to AQ - DQ flip-flops Delay from CE input to AQ - DQ flip-flops Toggle frequency (for export control) 0.41 1.81 0.53 862 0.48 1.81 0.65 806 0.65 2.50 0.92 667 1.58 3.05 1.36 ns, Min ns, Max ns, Max MHz Clock to AQ - DQ outputs 0.45 0.53 0.64 0.82 ns, Max An - Dn LUT inputs through F7AMUX or F7BMUX and F8MUX to BMUX output An - Dn LUT inputs through latch to AQ - DQ outputs An - Dn LUT inputs to AQ - DQ outputs (latch as logic) An LUT inputs to COUT output Bn LUT inputs to COUT output Cn LUT inputs to COUT output Dn LUT inputs to COUT output AX input to COUT output BX input to COUT output CX input to COUT output DX input to COUT output CIN input to COUT output CIN input to AMUX output CIN input to BMUX output CIN input to CMUX output CIN input to DMUX output 0.21 0.37 0.37 0.82 0.82 0.38 0.38 0.28 0.28 0.21 0.13 0.10 0.09 0.08 0.21 0.30 0.29 0.31 0.26 0.43 0.46 0.95 0.95 0.48 0.49 0.33 0.35 0.26 0.16 0.12 0.11 0.10 0.22 0.31 0.31 0.32 0.38 0.61 0.65 1.28 1.28 0.72 0.71 0.49 0.48 0.40 0.24 0.18 0.14 0.13 0.29 0.46 0.41 0.44 0.49 0.80 0.86 1.70 1.70 0.95 0.92 0.67 0.63 0.51 0.35 0.18 0.18 0.11 0.47 0.58 0.59 0.67 ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max ns, Max
Description
Speed Grade -4 -3 -2 -1L
Units
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK AX - DX input to CLK on A - D flip-flops CE input to CLK on A - D flip-flops SR input to CLK on A - D flip-flops CIN input to CLK on A - D flip-flops 0.42 0.28 0.31 -0.07 0.34 0.02 0.31 -0.17 0.47 0.39 0.37 -0.07 0.42 0.02 0.31 -0.13 0.74 0.54 0.59 -0.07 0.49 0.02 0.49 -0.12 0.99 0.58 0.59 -0.27 0.63 -0.33 0.79 -0.46 ns, Min ns, Min ns, Min ns, Min
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 40: CLB Distributed RAM Switching Characteristics (SLICEM Only)
Symbol
Sequential Delays TSHCKO Clock to A - D outputs Clock to A - D outputs (direct output path) Setup and Hold Times Before/After Clock CLK TDS/TDH TAS/TAH TWS/TWH TCECK/TCKCE AX - DX or AI - DI inputs to CLK Address An inputs to clock WE input to clock CE input to CLK 0.59 0.17 0.28 0.35 0.31 -0.08 0.31 -0.08 0.73 0.22 0.32 0.42 0.37 -0.08 0.37 -0.08 1.04 0.37 0.40 0.67 0.59 -0.08 0.59 -0.08 1.17 0.33 0.26 0.71 0.59 -0.27 0.59 -0.27 ns, Min ns, Min ns, Min ns, Min 1.26 0.96 1.55 1.20 2.12 1.60 2.56 ns, Max ns, Max
Description
Speed Grade -4 -3 -2 -1L
Units
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 41: CLB Shift Register Switching Characteristics
Symbol
Sequential Delays TREG Clock to A - D outputs Clock to A - D outputs (direct output path) Setup and Hold Times Before/After Clock CLK TWS/TWH TCECK/TCKCE TDS/TDH WE input to CLK CE input to CLK AX - DX or AI - DI inputs to CLK 0.20 -0.07 0.27 0.36 0.07 0.11 0.24 -0.07 0.29 0.38 0.09 0.14 0.36 -0.07 0.52 0.40 0.18 0.28 0.59 -0.17 0.59 -0.17 1.16 0.28 ns, Min ns, Min ns, Min 1.35 1.24 1.78 1.65 2.14 1.95 2.89 ns, Max ns, Max
Description
Speed Grade -4 -3 -2 -1L
Units
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Block RAM Switching Characteristics
Table 42: Block RAM Switching Characteristics
Symbol
Block RAM Clock to Out Delays TRCKO_DO TRCKO_DO_REG TRCCK_ADDR/TRCKC_ADDR TRDCK_DI/TRCKD_DI TRCCK_EN/TRCKC_EN TRCCK_REGCE/TRCKC_REGCE TRCCK_WE/TRCKC_WE Maximum Frequency FMAX Block RAM in all modes 320 280 260 150 MHz Clock CLK to DOUT output (without output register)(1) Clock CLK to DOUT output (with output register)(2) 1.85 1.60 2.10 1.75 2.90 1.90 3.50 2.30 ns, Max ns, Max
Description
Speed Grade -4 -3 -2 -1L
Units
Setup and Hold Times Before/After Clock CLK ADDR inputs(3) DIN inputs (4) Block RAM Enable (EN) input CE input of output register Write Enable (WE) input 0.35 0.10 0.30 0.10 0.21 0.05 0.20 0.10 0.25 0.10 0.40 0.12 0.30 0.10 0.22 0.06 0.20 0.10 0.33 0.10 0.40 0.15 0.30 0.12 0.28 0.10 0.25 0.12 0.46 0.12 0.50 0.15 0.40 0.15 0.26 0.10 0.28 0.15 0.28 0.15 ns, Min ns, Min ns, Min ns, Min ns, Min
Notes: 1. TRCKO_DO includes TRCKO_DOA and TRCKO_DOPA as well as the B port equivalent timing parameters. 2. TRCKO_DO_REG includes TRCKO_DOA_REG and TRCKO_DOPA_REG as well as the B port equivalent timing parameters. 3. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible. 4. TRDCK_DI includes both A and B inputs as well as the parity inputs of A and B.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DSP48A1 Switching Characteristics
Table 43: DSP48A1 Switching Characteristics
Symbol Description Preadder Multiplier Postadder Speed Grade
-4 -3 -2 -1L
Units
Setup and Hold Times of Data/Control Pins to the Input Register Clock TDSPDCK_A_A1REG/ TDSPCKD_A_A1REG TDSPDCK_D_B1REG/ TDSPCKD_D_B1REG TDSPDCK_C_CREG/ TDSPCKD_C_CREG TDSPDCK_D_DREG/ TDSPCKD_D_DREG TDSPDCK_OPMODE_B1REG/ TDSPCKD_OPMODE_B1REG A input to A1 register CLK D input to B1 register CLK C input to C register CLK D input to D register CLK OPMODE input to B1 register CLK N/A Yes N/A N/A Yes N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.15 0.09 1.90 -0.07 0.11 0.15 0.09 0.15 1.97 0.01 0.18 0.12 0.17 0.09 1.95 -0.07 0.13 0.15 0.10 0.15 2.00 0.01 0.21 0.12 0.23 0.09 1.99 -0.07 0.17 0.15 0.14 0.15 2.01 0.01 0.28 0.26 0.32 0.09 2.82 -0.07 0.24 0.09 0.19 0.12 2.85 0.01 0.40 0.12 ns ns ns ns ns ns
TDSPDCK_OPMODE_OPMODEREG/ OPMODE input to TDSPCKD_OPMODE_OPMODEREG OPMODE register CLK TDSPDCK_A_MREG/ TDSPCKD_A_MREG TDSPDCK_B_MREG/ TDSPCKD_B_MREG TDSPDCK_D_MREG/ TDSPCKD_D_MREG TDSPDCK_OPMODE_MREG/ TDSPCKD_OPMODE_MREG A input to M register CLK B input to M register CLK D input to M register CLK OPMODE to M register CLK
Setup and Hold Times of Data Pins to the Pipeline Register Clock N/A Yes Yes Yes No Yes Yes Yes Yes Yes N/A N/A N/A N/A N/A 3.06 -0.40 3.96 -0.68 4.23 -0.56 4.18 -0.48 2.37 -0.48 3.51 -0.40 4.58 -0.68 4.80 -0.56 4.80 -0.48 2.70 -0.48 3.71 -0.40 5.28 -0.68 4.82 -0.56 4.85 -0.48 3.02 -0.48 3.97 -0.40 7.00 -0.68 6.84 -0.56 6.88 -0.48 4.28 -0.48 ns ns ns ns ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock TDSPDCK_A_PREG/ TDSPCKD_A_PREG TDSPDCK_B_PREG/ TDSPCKD_B_PREG A input to P register CLK B input to P register CLK N/A Yes No TDSPDCK_C_PREG/ TDSPCKD_C_PREG TDSPDCK_D_PREG/ TDSPCKD_D_PREG TDSPDCK_OPMODE_PREG/ TDSPCKD_OPMODE_PREG C input to P register CLK D input to P register CLK OPMODE input to P register CLK N/A Yes Yes No No Yes Yes Yes N/A Yes Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes 4.32 -0.76 5.87 -0.59 4.14 -0.93 2.20 -0.23 5.90 -0.92 6.21 -0.84 1.69 -0.87 2.09 -0.22 5.06 -0.76 6.87 -0.59 4.68 -0.93 2.25 -0.23 6.91 -0.92 7.27 -0.84 1.98 -0.87 2.30 -0.22 5.38 -0.76 7.87 -0.59 6.16 -0.93 2.30 -0.23 7.32 -0.92 7.35 -0.84 2.55 -0.87 2.67 -0.22 7.52 -0.76 10.55 -0.59 8.12 -0.93 3.27 -0.23 10.39 -0.92 10.43 -0.84 3.62 -0.87 3.79 -0.22 ns ns ns ns ns ns ns ns
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 43: DSP48A1 Switching Characteristics (Cont'd)
Symbol Description Preadder Multiplier Postadder Speed Grade
-4 -3 -2 -1L
Units
Clock to Out from Output Register Clock to Output Pin TDSPCKO_P_PREG TDSPCKO_P_MREG TDSPCKO_P_A1REG TDSPCKO_P_B1REG TDSPCKO_P_CREG TDSPCKO_P_DREG TDSPDO_A_P CLK (PREG) to P output N/A N/A N/A 1.20 1.34 1.34 1.90 ns
Clock to Out from Pipeline Register Clock to Output Pins CLK (MREG) to P output N/A N/A Yes 3.38 3.95 4.19 5.83 ns
Clock to Out from Input Register Clock to Output Pins CLK (A1REG) to P output CLK (B1REG) to P output CLK (CREG) to P output CLK (DREG) to P output N/A N/A N/A Yes Yes Yes N/A Yes Yes Yes Yes Yes 5.02 5.02 3.12 6.77 5.87 5.87 3.64 7.92 6.80 6.79 3.70 9.06 9.65 9.63 5.24 12.53 ns ns ns ns
Combinatorial Delays from Input Pins to Output Pins A input to P output N/A N/A N/A TDSPDO_B_P B input to P output Yes Yes Yes TDSPDO_C_P TDSPDO_D_P TDSPDO_OPMODE_P C input to P output D input to P output OPMODE input to P output N/A Yes Yes No No Maximum Frequency FMAX All registers used Yes Yes Yes 390 333 302 213 MHz No Yes Yes No Yes Yes N/A Yes Yes Yes No Yes No Yes No No Yes Yes Yes Yes Yes Yes 2.85 3.35 4.56 3.22 6.01 6.27 2.69 6.31 6.43 4.84 3.11 3.33 3.93 5.22 3.76 6.54 7.34 3.15 7.38 7.52 5.66 3.49 3.41 4.83 6.38 3.91 6.88 8.43 3.30 8.32 8.35 6.52 3.55 4.73 6.74 8.94 5.55 9.76 11.96 4.68 11.81 11.84 9.25 5.03 ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. A Yes signifies that the component is in the path. A No signifies that the component is being bypassed. N/A signifies not applicable because no path exists.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 44: Device DNA Interface Port Switching Characteristics
Symbol
TDNASSU TDNASH TDNADSU TDNADH TDNARSU TDNARH TDNADCKO TDNACLKF TDNACLKL TDNACLKH
(2)
Description
Setup time on SHIFT before the rising edge of CLK Hold time on SHIFT after the rising edge of CLK Setup time on DIN before the rising edge of CLK Hold time on DIN after the rising edge of CLK Setup time on READ before the rising edge of CLK Hold time on READ after the rising edge of CLK Clock-to-output delay on DOUT after rising edge of CLK CLK frequency CLK Low time CLK High time
Speed Grade -4 -3
7 1 7 1 7 1,000 1 0.5 6 2 50 50
-2
-1L
Units
ns, Min ns, Min ns, Min ns, Min ns, Min ns, Max ns, Min ns, Min ns, Max MHz, Max ns, Min ns, Min
Notes: 1. The minimum READ pulse width is 8 ns, the maximum READ pulse width is 1 s. 2. Also applies to TCK when reading DNA through the boundary-scan port.
Table 45: Suspend Mode Switching Characteristics
Symbol
Entering Suspend Mode TSUSPENDHIGH_AWAKE TSUSPENDFILTER TSUSPEND_GWE TSUSPEND_GTS TSUSPEND_DISABLE Exiting Suspend Mode TSUSPENDLOW_AWAKE TSUSPEND_ENABLE TAWAKE_GWE1 TAWAKE_GWE512 TAWAKE_GTS1 TAWAKE_GTS512 TSCP_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not include DCM or PLL lock time. Falling edge of the SUSPEND pin to FPGA input pins and interconnect reenabled Rising edge of the AWAKE pin until write-protect lock released on all writable clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1. Rising edge of the AWAKE pin until write-protect lock released on all writable clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512. Rising edge of the AWAKE pin until outputs return to the behavior described in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1. Rising edge of the AWAKE pin until outputs return to the behavior described in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512. Rising edge of SCP pins to rising edge of AWAKE pin 7 7 - - - - 7 75 41 80 20.5 80 20.5 75 s s ns s ns s s Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled Rising edge of SUSPEND pin until FPGA output pins drive their defined SUSPEND constraint behavior (without glitch filter) Rising edge of SUSPEND pin to write-protect lock on all writable clocked elements (without glitch filter) Rising edge of the SUSPEND pin to FPGA input pins and interconnect disabled (without glitch filter) 2.5 31 - - - 14 430 15 15 1500 ns ns ns ns ns
Description
Min
Max
Units
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Configuration Switching Characteristics
Table 46: Configuration Switching Characteristics(1)
Symbol
Power-up Timing Characteristics TPL(2) TPOR(2) TPROGRAM TDCCK/TCCKD TCCO FSCCK TSMDCCK/TSMCCKD TSMCSCCK/TSMCCKCS TSMCCKW/TSMWCCK TSMCKCSO TSMCO TSMCKBY PROGRAM_B Latency Power-on-Reset PROGRAM_B Pulse Width 4 5/40 500 4 5/40 500 4 5/40 500 5 5/40 500 ms, Max ms, Min/Max ns, Min
Description
Speed Grade -4 -3 -2 -1L
Units
Slave Serial Mode Programming Switching DIN Setup/Hold, slave mode CCLK to DOUT Slave mode external CCLK 6.0/1.0 12 80 6.0/1.0 12 80 6.0/1.0 12 80 8.0/2.0 17 50 ns, Min ns, Max MHz, Max
Slave SelectMAP Mode Programming Switching SelectMAP Data Setup/Hold CSI_B Setup/Hold RDWR_B Setup/Hold CSO_B clock to out CCLK to DATA out in readback CCLK to BUSY out in readback Maximum CCLK frequency (XC6SLX4, XC6SLX9, XC6SLX16, XC6SLX25, XC6SLX25T, XC6SLX45, XC6SLX45T, XC6SLX75, and XC6SLX75T only) Maximum CCLK frequency (XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) Maximum Readback CCLK frequency (XC6SLX4, XC6SLX9, XC6SLX16, XC6SLX25, XC6SLX25T, XC6SLX45, XC6SLX45T, XC6SLX75, and XC6SLX75T only) Maximum Readback CCLK frequency (XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T only) Boundary-Scan Port Timing Specifications TTAPTCK TTCKTAP TTCKTDO TTCKH TTCKL FTCK FTCKB FTCKAES TMS and TDI Setup time before TCK TMS and TDI Hold time after TCK TCK falling edge to TDO output valid TCK clock minimum High time TCK clock minimum Low time Maximum configuration TCK clock frequency Maximum boundary-scan TCK clock frequency Maximum AES key TCK clock frequency 10 5.5 6.5 12 12 33 33 2 10 5.5 6.5 12 12 33 33 2 10 5.5 6.5 12 12 33 33 2 17 5.5 8 21 21 18 18 2 ns, Min ns, Min ns, Max ns, Min ns, Min MHz, Max MHz, Max MHz, Max 6.0/1.0 7.0/0.0 6.0/1.0 7.0/0.0 6.0/1.0 7.0/0.0 8.0/2.0 9.0/2.0 ns, Min ns, Min ns, Min ns, Min ns, Max ns, Max MHz, Max
17.0/1.0 17.0/1.0 17.0/1.0 27.0/2.0 16 13 12 50 16 13 12 50 16 13 12 50 26 25 17 25
FSMCCK
40
40
40
20
MHz, Max
20
20
20
4
MHz, Max
FRBCCK
12
12
12
4
MHz, Max
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 46: Configuration Switching Characteristics(1) (Cont'd)
Symbol Description Speed Grade -4 -3 -2 -1L Units
BPI Master Flash Mode Programming Switching(3) TBPICCO(4) TBPIICCK TBPIDCC/TBPICCD TSPIDCC/TSPIDCCD A[25:0], FCS_B, FOE_B, FWE_B, LDC outputs valid after CCLK falling edge Master BPI CCLK (output) delay Setup/Hold on D[15:0] data input pins 15 10/100 5.0/1.0 15 10/100 5.0/1.0 15 10/100 5.0/1.0 20 10/130 6.0/2.0 ns, Min s, Min/Max ns, Min
SPI Master Flash Mode Programming Switching DIN, MISO0, MISO1, MISO2, MISO3, Setup/Hold before/after the rising CCLK edge Master SPI CCLK (output) delay MOSI clock to out CSO_B clock to out 5.0/1.0 5.0/1.0 5.0/1.0 7.0/1.0 ns, Min
TSPIICCK TSPICCM TSPICCFC CCLK Output (Master Modes) TMCCKL TMCCKH FMCCK FMCCKTOL CCLK Input (Slave Modes) TSCCKL TSCCKH USERCCLK Input TUSERCCLKL TUSERCCLKH FUSERCCLK Notes:
1.
2. 3.
0.4/7.0 13 16
0.4/7.0 13 16
0.4/7.0 13 16
0.4/10.0 s, Min/Max 19 26 ns, Max ns, Max
Master CCLK clock duty cycle Low Master CCLK clock duty cycle High Maximum Frequency, master mode Frequency Tolerance, master mode 40 50 40 50
40/60 40/60 40 50 30 50
%, Min/Max %, Min/Max MHz, Max %
Slave CCLK clock minimum Low time Slave CCLK clock minimum High time
5 5
5 5
5 5
8 8
ns, Min ns, Min
USERCCLK clock minimum Low time USERCCLK clock minimum High time Maximum USERCCLK frequency
12 12 40
12 12 40
12 12 40
21 21 30
ns, Min ns, Min MHz, Max
4.
Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages. To support longer delays in configuration, use the design solutions described in the Spartan-6 FPGA Configuration User Guide. BPI mode is not supported in: * LX4, LX25, or LX25T devices * LX9 devices in the TQG144 package * LX9 or LX16 devices in the CPG196 package. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 47: Global Clock Switching Characteristics
Symbol
TGSI
Description
S pin Setup to I0/I1 inputs
Devices
LX Family LXT Family
Speed Grade -4
N/A 0.25 N/A 0.21
-3
0.31 0.31 0.21 0.21
-2
0.48 0.48 0.21 0.21
-1L
0.60 N/A
Units
ns ns ns
TGIO Maximum Frequency FMAX
BUFGMUX delay from I0/I1 to O
LX Family LXT Family
N/A
ns
Global clock tree (BUFG)
LX Family LXT Family
N/A 400
400 400
375 375 N/A
MHz MHz
Table 48: Input/Output Clock Switching Characteristics (BUFIO2)
Symbol
TBUFCKO_O Maximum Frequency FMAX I/O clock tree (BUFIO2) LX Family LXT Family N/A 540 525 525 500 500 N/A MHz MHz
Description
Clock to out delay from I to O
Devices
LX Family LXT Family
Speed Grade -4
N/A 0.67
-3
0.82 0.82
-2
1.09 1.09
-1L
1.80 N/A
Units
ns ns
Table 49: Input/Output Clock Switching Characteristics (BUFPLL)
Symbol
Maximum Frequency FMAX BUFPLL clock tree (BUFPLL) LX Family LXT Family N/A 1080 1050 1050 950 950 N/A MHz MHz
Description
Devices
Speed Grade -4 -3 -2 -1L
Units
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
PLL Switching Characteristics
Table 50: PLL Specification
Symbol
FINMAX
Description
Maximum Input Clock Frequency from I/O Clock Maximum Input Clock Frequency from Global Clock
Device(1) -4
LX Family LXT Family LX Family LXT Family LX Family LXT Family N/A 540 N/A 400 N/A 19
Speed Grade -3
525 525 400 400 19 19
Units -1L
MHz N/A MHz MHz N/A MHz MHz N/A MHz
-2
450 450 375 375 19 19
FINMIN FINJITTER FINDUTY
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter Allowable Input Duty Cycle: 19--199 MHz
All All
<20% of clock input period or 1 ns Max 25/75 35/65 45/55 N/A 400 N/A 1080 1 4 0.12 400 400 1050 1050 1 4 0.12 400 400 1000 1000 1 4 0.12 Note 2 0.15 100 N/A 400 N/A 1080 3.125 0.15 100 400 400 1050 1050 3.125 0.20 100 375 375 950 950 3.125 N/A 3.125 N/A 100 ns s MHz MHz MHz MHz MHz 400 N/A 1000 N/A 1 4 % % % MHz MHz MHz MHz MHz MHz ns
Allowable Input Duty Cycle: 200--299 MHz All Allowable Input Duty Cycle: > 300 MHz FVCOMIN FVCOMAX FBANDWIDTH TSTAPHAOFFSET TOUTJITTER TOUTDUTY TLOCKMAX FOUTMAX FOUTMAX FOUTMIN TEXTFDVAR RSTMINPULSE FPFDMAX(5) FPFDMIN TFBDELAY Minimum PLL VCO Frequency All LX Family LXT Family Maximum PLL VCO Frequency Typical(3) Typical(3) LX Family LXT Family Low PLL Bandwidth at High PLL Bandwidth at Jitter(3) Precision(4) All All All All All All LX Family LXT Family LX Family LXT Family All All All LX Family LXT Family LX Family LXT Family All
Static Phase Offset of the PLL Outputs PLL Output
PLL Output Clock Duty Cycle PLL Maximum Lock Time
PLL Maximum Output Frequency for BUFGMUX PLL Maximum Output Frequency for BUFPLL PLL Minimum Output Frequency(5)
External Clock Feedback Variation Minimum Reset Pulse Width Maximum Frequency at the Phase Frequency Detector Minimum Frequency at the Phase Frequency Detector Maximum Delay in the Feedback Path
< 20% of clock input period or 1 ns Max 5 N/A 500 N/A 19 5 500 500 19 19 5 400 400 19 19 N/A N/A 5 ns MHz MHz MHz MHz
3 ns Max or one CLKIN cycle
Notes: 1. LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade. 2. Values for this parameter are available in the Clocking Wizard. 3. The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies. 4. Includes global clock buffer. 5. Calculated as FVCO/128 assuming output duty cycle is 50%. 6. When using CLK_FEEDBACK = CLKOUT0 with BUFIO2 feedback, the feedback frequency will be higher than the phase frequency detector frequency. FPFDMAX = FCLKFB / CLKFBOUT_MULT
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DCM Switching Characteristics
Table 51: Operating Frequency Ranges and Conditions for the Delay-Locked Loop (DLL)(1)
Speed Grade Symbol Description Min
Input Frequency Ranges CLKIN_FREQ_DLL Input Pulse Requirements CLKIN_PULSE CLKIN pulse width as a percentage of the CLKIN period for CLKIN_FREQ_DLL < 150 MHz CLKIN pulse width as a percentage of the CLKIN period for CLKIN_FREQ_DLL > 150 MHz Input Clock Jitter Tolerance and Delay Path Variation(4) CLKIN_CYC_JITT_DLL_LF Cycle-to-cycle jitter at the CLKIN input for CLKIN_FREQ_DLL < 150 MHz Cycle-to-cycle jitter at the CLKIN input for CLKIN_FREQ_DLL > 150 MHz. Period jitter at the CLKIN input. Allowable variation of the off-chip feedback delay from the DCM output to the CLKFB input. - 300 - 300 - 300 - 300 ps Frequency of the CLKIN clock input. Also described as FCLKIN. 5(2) 280(3) 5(2) 280(3) 5(2) 250(3) 5(2) 175(3) MHz
-4 Max Min
-3 Max Min
-2 Max Min
-1L Max
Units
40
60
40
60
40
60
40
60
%
45
55
45
55
45
55
45
55
%
CLKIN_CYC_JITT_DLL_HF
- - -
150 1 1
- - -
150 1 1
- - -
150 1 1
- - -
150 1 1
ps ns ns
CLKIN_PER_JITT_DLL CLKFB_DELAY_VAR_EXT
Notes: 1. DLL specifications apply when using any of the DLL outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV. 2. When operating independently of the DLL, the DFS supports lower CLKIN_FREQ_DLL frequencies. See Table 53. 3. The CLKIN_DIVIDE_BY_2 attribute can be used to increase the effective input frequency range up to the FMAX for the global clock BUFG, see Table 47. When set to TRUE, the CLKIN_DIVIDE_BY_2 attribute divides the incoming clock frequency by two as it enters the DCM. 4. CLKIN_FREQ_DLL input jitter beyond these limits can cause the DCM to lose LOCK, indicated by the LOCKED output deasserting. The user must then reset the DCM. 5. When using both DCMs in a CMT, both DCMs must be LOCKED.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 52: Switching Characteristics for the Delay-Locked Loop (DLL)(1)
Speed Grade Symbol Description Min Output Frequency Ranges
CLKOUT_FREQ_CLK0 CLKOUT_FREQ_CLK90 CLKOUT_FREQ_2X CLKOUT_FREQ_DV Frequency for the CLK0 and CLK180 outputs. Frequency for the CLK90 and CLK270 outputs. Frequency for the CLK2X and CLK2X180 outputs. Frequency for the CLKDV output. 5 5 10
0.3125
-4 Max Min
-3 Max Min
-2 Max Min
-1L Max
Units
280 200 375 186
5 5 10
0.3125
280 200 375 186
5 5 10
0.3125
250 200 334 166
MHz MHz MHz MHz
Output Clock
Jitter(2)(3)(4)
Period jitter at the CLK0 output. Period jitter at the CLK90 output. Period jitter at the CLK180 output. Period jitter at the CLK270 output. Period jitter at the CLK2X and CLK2X180 outputs. Period jitter at the CLKDV output when performing integer division. Period jitter at the CLKDV output when performing non-integer division. - - - - - 100 150 150 150 - - - - 100 150 150 150 - - - - 100 150 150 150 - - - - ps ps ps ps ps ps
CLKOUT_PER_JITT_0 CLKOUT_PER_JITT_90 CLKOUT_PER_JITT_180 CLKOUT_PER_JITT_270 CLKOUT_PER_JITT_2X CLKOUT_PER_JITT_DV1 CLKOUT_PER_JITT_DV2
Maximum = [0.5% of CLKIN period + 100] 150 - 150 - 150
Maximum = [0.5% of CLKIN period + 100]
ps
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV outputs, including the BUFGMUX and clock tree duty-cycle distortion.
Typical = [1% of CLKIN period + 350]
ps
Phase Alignment(4)
CLKIN_CLKFB_PHASE Phase offset between the CLKIN and CLKFB inputs (CLK_FEEDBACK = 1X). Phase offset between the CLKIN and CLKFB inputs (CLK_FEEDBACK = 2X). CLKOUT_PHASE_DLL Phase offset between DLL outputs for CLK0 to CLK2X (not CLK2X180). Phase offset between DLL outputs for all others. - 150 - 150 - 150 - 250 ps Max - 250 - 250 - 250
Maximum = [1% of CLKIN period + 100] Maximum = [1% of CLKIN period + 150]
ps ps
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 52: Switching Characteristics for the Delay-Locked Loop (DLL)(1) (Cont'd)
Speed Grade Symbol
LOCK_DLL(3)
Description Min
When using the DLL alone: The time from deassertion at the DCM's reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase. 5 MHz < CLKIN_FREQ_DLL < 50 MHz. When using the DLL alone: The time from deassertion at the DCM's reset input to the rising transition at its LOCKED output. When the DCM is locked, the CLKIN and CLKFB signals are in phase. CLKIN_FREQ_DLL > 50 MHz
-4 Max Min
-3 Max Min
-2 Max Min
-1L Max
Units
-
5
-
5
-
5
-
5
ms
-
0.60
-
0.60
-
0.60
-
0.60
ms
Delay Lines
DCM_DELAY_STEP(5) Finest delay resolution, averaged over all steps. 10 40 10 40 10 40 10 40 ps
Notes: 1. The values in this table are based on the operating conditions described in Table 2 and Table 51. 2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input. 3. For optimal jitter tolerance and faster LOCK time, use the CLKIN_PERIOD attribute. 4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, this data sheet specifies a maximum jitter of (1% of CLKIN period + 150 ps). Assuming that the CLKIN frequency is 100 MHz, the equivalent CLKIN period is 10 ns. Since 1% of 10 ns is 0.1 ns or 100 ps, the maximum jitter is (100 ps + 150 ps) = 250 ps. 5. A typical delay step size is 23 ps.
Table 53: Recommended Operating Conditions for the Digital Frequency Synthesizer (DFS)(1)
Speed Grade Symbol Input Frequency Ranges(2)
CLKIN_FREQ_FX Frequency for the CLKIN input. Also described as FCLKIN. Cycle-to-cycle jitter at the CLKIN input, based on CLKFX output frequency: FCLKFX < 150 MHz. 0.5 375 0.5 375 0.5 333 MHz
Description Min
-4 Max Min
-3 Max Min
-2 Max
-1L Min Max
Units
Input Clock Jitter Tolerance(3)
CLKIN_CYC_JITT_FX_LF - 300 - 300 - 300 - 300 ps
CLKIN_CYC_JITT_FX_HF Cycle-to-cycle jitter at the CLKIN input, based on CLKFX output frequency: FCLKFX > 150 MHz. CLKIN_PER_JITT_FX Period jitter at the CLKIN input.
- -
150 1
- -
150 1
- -
150 1
- -
150 1
ps ns
Notes: 1. DFS specifications apply when using either of the DFS outputs (CLKFX or CLKFX180). 2. When using both DFS and DLL outputs on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 51. 3. CLKIN input jitter beyond these limits can cause the DCM to lose LOCK.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 54: Switching Characteristics for the Digital Frequency Synthesizer (DFS) for DCM_SP(1)
Speed Grade Symbol Description Min Output Frequency Ranges
CLKOUT_FREQ_FX Frequency for the CLKFX and CLKFX180 outputs 5 375 5 375 5 333 MHz
-4 Max Min
-3 Max Min
-2 Max
-1L Min Max
Units
Output Clock Jitter(2)(3)
Period jitter at the CLKFX and CLKFX180 outputs. When CLKIN < 20 MHz Period jitter at the CLKFX and CLKFX180 outputs. When CLKIN > 20 MHz Use the Clocking Wizard ps
CLKOUT_PER_JITT_FX
Typical = (1% of CLKFX period + 100)
ps
Duty Cycle(4)(5)
Duty cycle precision for the CLKFX and CLKFX180 outputs including the CLKOUT_DUTY_CYCLE_FX BUFGMUX and clock tree duty-cycle distortion Maximum = (1% of CLKFX period + 350) ps
Phase Alignment(5)
CLKOUT_PHASE_FX Phase offset between the DFS CLKFX output and the DLL CLK0 output when both the DFS and DLL are used Phase offset between the DFS CLKFX180 output and the DLL CLK0 output when both the DFS and DLL are used - 200 - 200 - 200 - 250 ps
CLKOUT_PHASE_FX180
Maximum = (1% of CLKFX period + 200)
ps
LOCKED Time
When 5 MHz < FCLKIN < 50 MHz, the time from deassertion at the DCM's reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 signals are valid. When using both the DLL and the DFS, use the longer locking time. When FCLKIN > 50 MHz, the time from deassertion at the DCM's reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 signals are valid. When using both the DLL and the DFS, use the longer locking time.
-
5
-
5
-
5
-
5
ms
LOCK_FX(2)
-
0.45
-
0.45
-
0.45
-
0.60
ms
Notes: 1. The values in this table are based on the operating conditions described in Table 2 and Table 53. 2. For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute. 3. Output jitter is characterized with no input jitter. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply, and PCB design. The actual maximum output jitter depends on the system application. 4. The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%. 5. Some duty cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum CLKFX jitter of (1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and 1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is (100 ps + 200 ps) = 300 ps.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 55: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN)(1)
Speed Grade Symbol Description Min Output Frequency Ranges (DCM_CLKGEN)
CLKOUT_FREQ_FX CLKOUT_FREQ_FXDV Frequency for the CLKFX and CLKFX180 outputs Frequency for the CLKFXDV output 5 375 5 375 5 333 5 200 100 MHz MHz
-4 Max Min
-3 Max Min
-2 Max Min
-1L Max
Units
0.15625 187.5 0.15625 187.5 0.15625 166.5 0.15625
Output Clock Jitter(2)(3)
CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180 outputs. Typical = [0.2% of CLKFX period + 100] Typical = [0.2% of CLKFX period + 100] ps ps
CLKOUT_PER_JITT_FXDV Period jitter at the CLKFXDV output. CLKFX period change in free running oscillator mode at the same temperature. FCLKFX > 50 MHz CLKFX period change in free running oscillator mode at the same temperature. FCLKFX < 50 MHz CLKFX period will change in free_oscillator mode over temperature. Add to CLKFX_FREEZE_VAR to determine total CLKFX period change. Percentage change for CLKFX period over 1C.
Maximum = 3% of CLKFX period
ps
CLKFX_FREEZE_VAR
Maximum = 5% of CLKFX period
ps
CLKFX_FREEZE_TEMP _SLOPE
Maximum = 0.1
%/C
Duty Cycle(4)(5)
CLKOUT_DUTY_CYCLE_ FX Duty cycle precision for the CLKFX and CLKFX180 outputs, including the BUFGMUX and clock tree duty-cycle distortion Duty cycle precision for the CLKFXDV outputs, including the BUFGMUX and clock tree duty-cycle distortion Maximum = [1% of CLKFX period + 350] ps
CLKOUT_DUTY_CYCLE_ FXDV
Maximum = [1% of CLKFX period + 350]
ps
Lock Time
LOCK_FX(2) The time from deassertion at the DCM's Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX, CLKFX180, and CLKFXDV signals are valid. Lock time requires CLKFX_DIVIDE < FIN/(0.50 MHz) when: 5 MHz < FCLKIN < 50 MHz when: FCLKIN > 50 MHz
-
50
-
50
-
50
-
50
ms
-
5
-
5
-
5
-
5
ms
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 55: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN)(1) (Cont'd)
Speed Grade Symbol Description Min Spread Spectrum
FCLKIN_FIXED_SPREAD_ SPECTRUM Frequency of the CLKIN input for fixed spread spectrum (SPREAD_SPECTRUM = CENTER_LOW_SPREAD/ CENTER_HIGH_SPREAD) Spread at the CLKFX output for fixed spread spectrum (SPREAD_SPECTRUM = CENTER_LOW_SPREAD) Spread at the CLKFX output for fixed spread spectrum (SPREAD_SPECTRUM= CENTER_HIGH_SPREAD) Average modulation frequency when using fixed spread spectrum (SPREAD_SPECTRUM = CENTER_LOW_SPREAD / CENTER_HIGH_SPREAD)
-4 Max Min
-3 Max Min
-2 Max Min
-1L Max
Units
30
200
30
200
30
200
30
200
MHz
TCENTER_LOW_SPREAD(6)
100 Typical = ----------------------------------------CLKFX_DIVIDE
Maximum = 250
240 Typical = ----------------------------------------CLKFX_DIVIDE
ps
TCENTER_HIGH_SPREAD(6)
ps
Maximum = 400
FMOD_FIXED_SPREAD_
SPECTRUM (6)
Typical = FIN/1024
MHz
Notes: 1. The values in this table are based on the operating conditions described in Table 2 and Table 53. 2. For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute. 3. Output jitter is characterized with no input jitter. Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency, power supply, and PCB design. The actual maximum output jitter depends on the system application. 4. The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%. 5. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum CLKFX jitter of (1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and 1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is (100 ps + 200 ps) = 300 ps. 6. When using CENTER_LOW_SPREAD, CENTER_HIGH_SPREAD, the valid values for CLKFX_MULTIPLY are limited to 2 through 32, and the valid values for CLKFX_DIVIDE are limited to 1 through 4.
Table 56: Recommended Operating Conditions for the Phase-Shift Clock in Variable Phase Mode
Speed Grade Symbol Description Min Operating Frequency Ranges
PSCLK_FREQ Frequency for the PSCLK input. 1 167 1 167 1 167 1 100 MHz
-4 Max Min
-3 Max Min
-2 Max Min
-1L Max
Units
Input Pulse Requirements
PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period. 40 60 40 60 40 60 40 60 %
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 57: Switching Characteristics for the Phase-Shift Clock in Variable Phase Mode(1)
Symbol Phase Shifting Range
When CLKIN < 60 MHz, the maximum allowed number of DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN clock period in ns. When using CLKIN_DIVIDE_BY_2 = TRUE, double the clock-effective clock period. When CLKIN 60 MHz, the maximum allowed number of DCM_DELAY_STEP steps for a given CLKIN clock period, where T = CLKIN clock period in ns. When using CLKIN_DIVIDE_BY_2 = TRUE, double the clock-effective clock period. Minimum guaranteed delay for variable phase shifting. Maximum guaranteed delay for variable phase shifting (INTEGER(10 x (TCLKIN - 3 ns))) steps
Description
Amount of Phase Shift
Units
MAX_STEPS(2)
(INTEGER(15 x (TCLKIN - 3 ns)))
steps
FINE_SHIFT_RANGE_MIN FINE_SHIFT_RANGE_MAX
(MAX_STEPS x DCM_DELAY_STEP_MIN) (MAX_STEPS x DCM_DELAY_STEP_MAX)
ns ns
Notes: 1. The values in this table are based on the operating conditions described in Table 51 and Table 56. 2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM has no initial fixed-phase shifting, that is, the PHASE_SHIFT attribute is set to 0. 3. The DCM_DELAY_STEP values are provided at the end of Table 52.
Table 58: Miscellaneous DCM Timing Parameters(1)
Symbol
DCM_RST_PW_MIN
Description
Minimum duration of a RST pulse width
Min
3
Max
-
Units
CLKIN cycles
Notes: 1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM DFS outputs (CLKFX, CLKFXDV, CLKFX180) are unaffected.
Table 59: Frequency Synthesis
Attribute
CLKFX_MULTIPLY (DCM_SP) CLKFX_DIVIDE (DCM_SP) CLKDV_DIVIDE (DCM_SP) CLKFX_MULTIPLY (DCM_CLKGEN) CLKFX_DIVIDE (DCM_CLKGEN) CLKFXDV_DIVIDE (DCM_CLKGEN)
Min
2 1 1.5 2 1 2
Max
32 32 16 256 256 32
Table 60: DCM Switching Characteristics
Symbol
TDMCCK_PSEN/ TDMCKC_PSEN TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC TDMCKO_PSDONE
Description
PSEN Setup/Hold PSINCDEC Setup/Hold Clock to out of PSDONE
Speed Grade -4
1.50 0.00 1.50 0.00 1.50
-3
1.50 0.00 1.50 0.00 1.50
-2
1.50 0.00 1.50 0.00 1.50
-1L
1.50 0.00 1.50 0.00 1.50
Units
ns ns ns
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Spartan-6 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 61 through Table 67. Values are expressed in nanoseconds unless otherwise noted. Table 61: Global Clock Input to Output Delay Without DCM or PLL
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL TICKOF Global Clock and OUTFF without DCM or PLL XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 6.20 N/A 6.42 N/A 6.60 N/A 6.72 N/A 7.11 6.48 6.34 6.42 6.69 6.69 6.88 6.88 7.22 7.22 7.18 7.18 7.68 7.68 7.44 7.33 7.48 7.84 7.84 8.10 8.10 8.42 8.42 8.41 8.41 8.80 8.80 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 62: Global Clock Input to Output Delay With DCM in System-Synchronous Mode
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode. TICKOFDCM Global Clock and OUTFF with DCM XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 3.95 N/A 4.37 N/A 3.90 N/A 3.90 N/A 4.03 4.50 4.50 4.57 4.18 4.18 4.70 4.70 4.23 4.23 4.16 4.16 4.33 4.33 5.32 5.31 5.34 4.59 4.59 5.50 5.50 4.77 4.77 4.66 4.66 4.83 4.83 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 63: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode. TICKOFDCM_0 Global Clock and OUTFF with DCM XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 4.81 N/A 5.26 N/A 4.77 N/A 4.76 N/A 4.90 5.44 5.43 5.51 5.13 5.13 5.69 5.69 5.18 5.18 5.11 5.11 5.30 5.30 6.42 6.42 6.44 5.69 5.69 6.63 6.63 5.88 5.88 5.76 5.76 5.93 5.93 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM output jitter is already included in the timing calculation.
Table 64: Global Clock Input to Output Delay With PLL in System-Synchronous Mode
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in System-Synchronous Mode. TICKOFPLL Global Clock and OUTFF with PLL XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 4.03 N/A 4.63 N/A 4.01 N/A 4.06 N/A 3.65 4.69 4.68 4.64 4.32 4.32 4.96 4.96 4.30 4.30 4.33 4.33 3.98 3.98 5.48 5.47 5.39 4.91 4.91 5.75 5.75 4.88 4.88 4.90 4.90 4.58 4.58 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is included in the timing calculation.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 65: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode. TICKOFPLL_0 Global Clock and OUTFF with PLL XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 5.00 N/A 5.59 N/A 4.96 N/A 5.01 N/A 4.59 5.81 5.80 5.77 5.35 5.35 6.03 6.03 5.41 5.41 5.42 5.42 5.06 5.06 6.87 6.86 6.79 6.10 6.10 7.02 7.02 6.22 6.22 6.21 6.21 5.86 5.86 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. PLL output jitter is included in the timing calculation.
Table 66: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode and PLL in DCM2PLL Mode. TICKOFDCM_PLL Global Clock and OUTFF with DCM and PLL XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 4.70 N/A 4.63 N/A 4.68 N/A 4.76 N/A 4.44 5.01 5.01 5.12 5.09 5.09 4.98 4.98 5.04 5.04 5.07 5.07 4.73 4.73 5.90 5.89 5.94 5.92 5.92 5.83 5.83 5.88 5.88 5.92 5.92 5.31 5.31 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM and PLL output jitter are already included in the timing calculation.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 67: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode and PLL in DCM2PLL Mode. TICKOFDCM0_PLL Global Clock and OUTFF with DCM and PLL XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 5.57 N/A 5.53 N/A 5.55 N/A 5.62 N/A 5.32 5.95 5.94 6.06 6.04 6.04 5.97 5.97 6.00 6.00 6.03 6.03 5.70 5.70 7.00 7.00 7.05 7.02 7.02 6.96 6.96 6.99 6.99 7.02 7.02 6.41 6.41 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. 2. DCM and PLL output jitter are already included in the timing calculation.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Spartan-6 Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 68 through Table 74. Values are expressed in nanoseconds unless otherwise noted. Table 68: Global Clock Setup and Hold Without DCM or PLL
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSFD/ TPHFD Full Delay (Legacy Delay or Default Delay) XC6SLX4 Global Clock and IFF(2) without DCM or PLL XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 0.18/ 1.64 N/A -0.08/ 1.88 N/A 0.13/ 2.08 N/A -0.14/ 2.15 N/A -0.24/ 2.55 0.34/ 1.54 0.31/ 1.40 0.12/ 1.48 0.18/ 1.75 0.18/ 1.75 -0.08/ 1.95 -0.08/ 1.95 0.13/ 2.29 0.13/ 2.29 -0.14/ 2.24 -0.14/ 2.24 -0.24/ 2.74 -0.24/ 2.74 0.34/ 1.59 0.31/ 1.49 0.12/ 1.64 0.18/ 1.99 0.18/ 1.99 -0.08/ 2.27 -0.08/ 2.27 0.13/ 2.57 0.13/ 2.57 -0.14/ 2.56 -0.14/ 2.56 -0.24/ 2.95 -0.24/ 2.95 N/A N/A 0 N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. 2. IFF = Input Flip-Flop or Latch.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 69: Global Clock Setup and Hold With DCM in System-Synchronous Mode
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCM/ TPHDCM No Delay Global Clock and IFF(2) with DCM XC6SLX4 in System-Synchronous Mode XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 1.79/ 0.16 N/A 1.76/ 0.07 N/A 1.89/ 0.11 N/A 1.69/ 0.16 N/A 1.51/ 0.39 1.97/ 0.18 1.96/ 0.19 1.87/ -0.17 1.78/ 0.17 1.79/ 0.17 1.84/ 0.08 1.84/ 0.08 1.98/ 0.12 1.98/ 0.12 1.72/ 0.17 1.72/ 0.17 1.62/ 0.40 1.62/ 0.40 2.20/ 0.18 2.19/ 0.19 2.13/ -0.17 2.00/ 0.17 2.00/ 0.17 2.02/ 0.08 2.02/ 0.08 2.20/ 0.12 2.20/ 0.12 1.97/ 0.17 1.97/ 0.17 1.82/ 0.40 1.82/ 0.40 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 70: Global Clock Setup and Hold With DCM in Source-Synchronous Mode
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCM0/ TPHDCM0 No Delay Global Clock and IFF(2) with DCM XC6SLX4 in Source-Synchronous Mode XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 0.94/ 0.76 N/A 0.87/ 0.73 N/A 1.03/ 0.71 N/A 0.86/ 0.75 N/A 0.66/ 0.98 1.02/ 0.69 1.01/ 0.70 0.92/ 0.57 0.90/ 0.77 0.94/ 0.77 0.90/ 0.76 0.90/ 0.76 1.06/ 0.72 1.06/ 0.72 0.81/ 0.76 0.86/ 0.76 0.69/ 0.99 0.69/ 0.99 1.11/ 0.69 1.10/ 0.70 1.04/ 0.60 1.01/ 0.77 1.01/ 0.77 0.98/ 0.79 0.98/ 0.79 1.15/ 0.72 1.15/ 0.72 0.94/ 0.76 0.94/ 0.76 0.79/ 0.99 0.79/ 0.99 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 71: Global Clock Setup and Hold With PLL in System-Synchronous Mode
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSPLL/ TPHPLL No Delay Global Clock and IFF(2) with PLL in System-Synchronous Mode XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 1.70/ 0.28 N/A 1.57/ 0.18 N/A 1.80/ 0.21 N/A 1.51/ 0.32 N/A 1.41/ 0.49 2.07/ 0.19 2.06/ 0.20 1.53/ 0.07 1.71/ 0.28 1.71/ 0.28 1.64/ 0.18 1.64/ 0.18 1.89/ 0.21 1.89/ 0.21 1.52/ 0.32 1.52/ 0.32 1.48/ 0.49 1.48/ 0.49 2.07/ 0.19 2.06/ 0.20 1.60/ 0.07 1.91/ 0.28 1.91/ 0.28 1.75/ 0.18 1.75/ 0.18 2.13/ 0.21 2.13/ 0.21 1.70/ 0.32 1.70/ 0.32 1.67/ 0.49 1.67/ 0.49 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 72: Global Clock Setup and Hold With PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSPLL0/ TPHPLL0 No Delay Global Clock and IFF(2) with PLL in Source-Synchronous Mode XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 0.83/ 1.06 N/A 0.59/ 1.06 N/A 0.88/ 1.04 N/A 0.61/ 1.13 N/A 0.52/ 1.31 0.88/ 0.92 0.87/ 0.93 0.37/ 0.82 0.76/ 1.06 0.83/ 1.06 0.65/ 1.10 0.65/ 1.10 0.87/ 1.04 0.88/ 1.04 0.54/ 1.13 0.61/ 1.13 0.51/ 1.31 0.52/ 1.31 0.91/ 1.03 0.89/ 1.02 0.51/ 0.94 0.79/ 1.06 0.83/ 1.06 0.65/ 1.18 0.65/ 1.18 0.90/ 1.04 0.90/ 1.04 0.55/ 1.13 0.61/ 1.13 0.52/ 1.31 0.52/ 1.31 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 73: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSDCMPLL/ TPHDCMPLL No Delay Global Clock and IFF(2) with DCM in System-Synchronous Mode and PLL in DCM2PLL Mode. XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 1.69/ 0.42 N/A 1.57/ 0.39 N/A 1.74/ 0.41 N/A 1.46/ 0.51 N/A 1.35/ 0.69 2.06/ 0.87 2.05/ 0.88 1.49/ 0.18 1.65/ 0.42 1.69/ 0.42 1.59/ 0.39 1.59/ 0.39 1.80/ 0.41 1.80/ 0.41 1.46/ 0.51 1.46/ 0.51 1.40/ 0.69 1.40/ 0.69 2.30/ 0.87 2.29/ 0.88 1.62/ 0.18 1.83/ 0.42 1.83/ 0.42 1.75/ 0.39 1.75/ 0.39 1.99/ 0.41 1.99/ 0.41 1.64/ 0.51 1.64/ 0.51 1.55/ 0.69 1.55/ 0.69 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. 2. IFF = Input Flip-Flop or Latch 3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 74: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode
Symbol Description Device Speed Grade
-4 -3 -2
-1L
Units
Example Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin,(1) Using DCM, PLL, and Global Clock Buffer. For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in IOB Switching Characteristics, page 19. TPSDCMPLL_0/ TPHDCMPLL_0 No Delay Global Clock and IFF (2) with DCM XC6SLX4 in Source-Synchronous Mode and PLL in DCM2PLL Mode. XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 0.84/ 1.02 N/A 0.68/ 1.00 N/A 0.89/ 1.03 N/A 0.63/ 1.10 N/A 0.50/ 1.28 1.11/ 1.38 1.10/ 1.38 0.83/ 1.12 0.76/ 1.11 0.84/ 1.11 0.65/ 1.04 0.68/ 1.04 0.88/ 1.06 0.89/ 1.06 0.56/ 1.10 0.63/ 1.10 0.47/ 1.28 0.50/ 1.28 1.21/ 1.38 1.20/ 1.39 0.83/ 1.21 0.84/ 1.18 0.84/ 1.18 0.71/ 1.12 0.71/ 1.12 0.94/ 1.14 0.94/ 1.14 0.61/ 1.17 0.63/ 1.17 0.53/ 1.28 0.52/ 1.28 N/A N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package skew is not included in these measurements. 2. IFF = Input Flip-Flop
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Spartan-6 FPGA source-synchronous transmitter and receiver data-valid windows. Table 75: Duty Cycle Distortion and Clock-Tree Skew
Symbol
TDCD_CLK TCKSKEW
Description
Device(1)
Speed Grade -4
N/A 0.20 N/A N/A N/A N/A 0.26 N/A 0.20 N/A 0.56 N/A 0.22 N/A 0.39 N/A 0.25 N/A 0.06
-3
0.20 0.20 0.16 0.16 0.15 0.26 0.26 0.20 0.20 0.56 0.56 0.22 0.22 0.48 0.48 0.25 0.25 0.06 0.06
-2
0.20 0.20 0.16 0.16 0.15 0.26 0.26 0.20 0.20 0.56 0.56 0.22 0.22 0.48 0.48 0.25 0.25 0.06 0.06
-1L
Units
ns
Global Clock Tree Duty Cycle Distortion(2) LX Family LXT Family Global Clock Tree Skew(3) XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T
N/A ns ns ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns ns N/A ns N/A ns
TDCD_BUFIO2 TBUFIOSKEW
I/O clock tree duty cycle distortion
LX Family LXT Family
I/O clock tree skew across one clock region
LX Family LXT Family
Notes: 1. LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade. 2. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 3. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA Editor and Timing Analyzer tools to evaluate clock skew specific to your application.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 76: Package Skew
Symbol
TPKGSKEW Package
Description
Skew(1)(2)
Device
XC6SLX4
Package(3)
TQG144 CPG196 CSG225 TQG144 CPG196
Value
23 58 23 58 88 64 19 70 71 54 90 61 84 48 112 70 99 109 138 75 100 95 101 107 161 107 110 134 95 155 144 88 111 147 134
Units
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
XC6SLX9
CSG225 FT(G)256 CSG324 CPG196 CSG225 FT(G)256 CSG324 FT(G)256
XC6SLX16
XC6SLX25
CSG324 FG(G)484 CSG324 FG(G)484 CSG324 CSG484 FG(G)484 FG(G)676 CSG324
XC6SLX25T
XC6SLX45
XC6SLX45T
CSG484 FG(G)484 CSG484
XC6SLX75
FG(G)484 FG(G)676 CSG484
XC6SLX75T
FG(G)484 FG(G)676 CSG484
XC6SLX100
FG(G)484 FG(G)676 CSG484 FG(G)484 FG(G)676 FG(G)900
XC6SLX100T
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics Table 76: Package Skew (Cont'd)
Symbol
TPKGSKEW
Description
Package Skew(1)
Device
Package(3)
CSG484 FG(G)484 FG(G)676 FG(G)900 CSG484 FG(G)484 FG(G)676 FG(G)900
Value
84 103 115 121 83 88 141 120
Units
ps ps ps ps ps ps ps ps
XC6SLX150
XC6SLX150T
Notes: 1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from Pad to Ball. 2. Package delay information is available for these device/package combinations. This information can be used to deskew the package. 3. Some of these devices are available in both Pb and Pb-free (additional G) packages as standard ordering options.
Table 77: Sample Window
Symbol
TSAMP TSAMP_BUFIO2
Description
Sampling Error at Receiver Pins(2) Sampling Error at Receiver Pins using BUFIO2(3)
Device(1)
All All
Speed Grade -4
510 430
-3
510 430
-2
560 480
-1L
Units
ps ps
Notes: 1. LX devices are not available with a -4 speed grade; LXT devices are not available with a -1L speed grade. 2. This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 DCM jitter - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew. 3. This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the BUFIO2 clock network and IODELAY to capture the DDR input registers' edges of operation. These measurements do not include package or clock tree skew.
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 78: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out Using BUFIO2
Symbol Description Device Speed Grade -4 -3 -2 -1L Units
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO2 TPSCS/TPHCS IFF setup/hold using BUFIO2 clock XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T Pin-to-Pin Clock-to-Out Using BUFIO2 TICKOFCS OFF clock-to-out using BUFIO2 clock XC6SLX4 XC6SLX9 XC6SLX16 XC6SLX25 XC6SLX25T XC6SLX45 XC6SLX45T XC6SLX75 XC6SLX75T XC6SLX100 XC6SLX100T XC6SLX150 XC6SLX150T N/A N/A N/A N/A 5.53 N/A 5.76 N/A 5.94 N/A 6.09 N/A 6.29 5.16 5.38 5.70 6.00 6.00 6.18 6.18 6.46 6.46 6.53 6.53 6.69 6.69 6.15 6.41 6.67 7.02 7.02 7.22 7.22 7.57 7.57 7.60 7.60 7.81 7.81 N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns N/A N/A N/A N/A 0.28/ 1.08 N/A 0.42/ 1.23 N/A 0.38/ 1.53 N/A 0.06/ 1.54 N/A 0.04/ 1.73 0.86/ 0.23 0.73/ 0.44 0.55/ 0.75 0.28/ 1.12 0.28/ 1.12 0.44/ 1.29 0.44/ 1.29 0.38/ 1.63 0.38/ 1.63 0.06/ 1.63 0.06/ 1.63 0.04/ 1.75 0.04/ 1.75 1.01/ 0.35 0.83/ 0.57 0.69/ 0.83 0.28/ 1.24 0.28/ 1.24 0.50/ 1.40 0.50/ 1.40 0.38/ 1.84 0.38/ 1.84 0.06/ 1.87 0.06/ 1.87 0.04/ 1.98 0.04/ 1.98 N/A N/A N/A N/A ns ns ns ns ns ns ns ns ns ns ns ns ns
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Revision History
The following table shows the revision history for this document.
Date
06/24/09 08/26/09
Version
1.0 1.1 Initial Xilinx release.
Description of Revisions
Added VFS to Table 1and Table 2. Added RFUSE to Table 2. Added XC6SLX75 and XC6SLX75T to VBATT and IBATT in Table 1, Table 2, and Table 4. Corrected the quiescent supply current for the XC6SLX4 in Table 5. Updated Table 11. Removed DVPPIN from Figure 2. Removed FPCIECORE from Table 24 and added values to FPCIEUSER. Added more networking applications to Table 25. Updated values for TSUSPENDLOW_AWAKE, TSUSPEND_ENABLE, and TSCP_AWAKE in Table 45. Numerous changes to Table 46, page 45 including the addition of new values to various specifications, revising the TSMCKCSO description, and changing the units of TPOR. Also, removed Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK section from Table 46 and updated all the notes. In Table 50, added to FINMAX, revised FOUTMAX, and removed PLL Maximum Output Frequency for BUFIO2. Revised values for DCM_DELAY_STEP in Table 52. Updated CLKIN_FREQ_FX values in Table 53. Added -4 speed grade to entire document. Updated speed specification of -4, -3, -2 speed grades to version 1.03. Added -1L speed grade numbers per speed specification 1.00. Updated TSOL in Table 1. Added -1L rows for LVCMOS12, LVCMOS15, and LVCMOS18 in Table 9. Revised much of the detail in GTP Transceiver Specifications in Table 12 through Table 23. Added -2 data to Table 25. Updated FMAX in Table 43. Updated descriptions for TDNACLKL and TDNACLKH in Table 44 and revised values for all parameters. Removed TINITADDR from Table 46 and added new data. Updated values in Table 47 through Table 60. Added Table 49 (BUFPLL) and Table 55 (DCM_CLKGEN). Removed TLOCKMAX note from Table 50. Updated note 3 in Table 51. In Table 76: removed XC6SLX75CSG324 and XC6SLX75TCSG324; added XC6SLX75FG(G)484 and XC6SLX75FG(G)484. Production release of XC6SLX16 -2 speed grade devices. The changes to Table 26 and Table 27 includes updating this data sheet to the data in ISE v11.5 software with speed specification v1.06. Updated maximum of VIN and VTS and note 2 in Table 1. In Table 2, changed VIN, added IIN and note 5, revised notes 1, 6, and 7, and added note 8 to RFUSE. In Table 4, removed previous note 1 and added data to IRPU, IRPD, and IBATT, changed CIN, added RDT and RIN_TERM, and added note 2 and 3. Updated VCCO2 in Table 6. Added Table 7 and Table 8. Removed PCI66_3 from Table 9. Updated PCI33_3 and I2C in Table 9. Updated the description of Table 11. Completely updated Table 25. Updated Table 28 including adding values for PCI33_3. Updated VREF value for HSTL_III_18 in Table 30. Updates missing VREF values in Table 31. Added Simultaneously Switching Outputs, page 27. Removed TGSRQ and TRPW from Table 34 and Table 35. Also removed TDOQ from Table 35. Removed TISDO_DO and note 1 from Table 36. Removed TOSCCK_S and combinatorial section from Table 37. In Table 38, removed TIODDO_T and added new tap parameters and note 2. In Table 39, Table 40, and Table 41, made typographical edits and removed notes. Removed clock CLK section in Table 40. Removed clock CLK section and TREG_MUX and TREG_M31 in Table 41. Added block RAM FMAX values to Table 42. Updated values and added note 2 to Table 44. Added values to Table 45 and removed note 1. Numerous changes to Table 46. Completely updated Table 55. Revised data in Table 60. Removed note 3 from Table 68. Added values to Table 76. Added data to Table 77 and Table 78. Production release of XC6SLX45 -2 speed grade devices, which includes changes to Table 26 and Table 27 updating this data sheet to the data in ISE v11.5 software with speed specification v1.07. Fixed RIN_TERM description in Table 4. Added PCI66_3 to Table 7 and replaced note 1. Corrected note 1 and the V, Max for TMDS_33 in Table 8. In Table 10, added note 1 to LVPECL_33 and TMDS_33. Also updated specifications for TMDS_33. Updated the GTP Transceiver Specifications section including adding values to Table 16, Table 17, and Table 20 through Table 23. Added PCI66_3 back into Table 9, Table 28, Table 30, Table 31, and Table 33. Updated note 3 on Table 31. In Table 33, corrected some typographical errors and fixed SSO limits for bank1/3 in FG(G)484 package. Corrected TOSCKC_OCE in Table 37. In Table 55, updated CLKFX_FREEZE_VAR and CLKFX_FREEZE_TEMP_SLOPE and added typical values to TCENTER_LOW_SPREAD and TCENTER_HIGH_SPREAD. Updated and added values to Table 61 through Table 75, and Table 78. In Table 76, revised the XC6SLX16-CSG324 and the XC6SLX45-CSG484 and FG(G)484 values.
01/04/10
1.2
02/22/10
1.3
03/10/10
1.4
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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Date
06/14/10
Version
1.5
Description of Revisions
In Table 2, added note 5 and added temperature range to VFS and RFUSE. Removed speed grade delineation, revised IRPD description, and updated note 2 in Table 4. Added note 2 to Table 7. Added DIFF_MOBILE_DDR to Table 8 and Table 10. Added note 4 to Table 15. Changed minimum DVPPIN in Table 16. Updated FGTPDRPCLK in Table 19. Increased maximum TLLSKEW in Table 22. Updated descriptions and added data to Table 23. Removed note 1 and added new data to the Networking Applications section in Table 25. Updated Table 26 and Table 27 to the data in ISE v12.1 software with speed specification v1.08. In Table 28, added DIFF_MOBILE_DDR and updated -4 speed grade data. Updated the maximum I/O pairs per bank in Table 32. Updated note 2 on Table 38. Revised the FMAX in Table 43. In Table 46, updated description for TSMCKCSO, revised values for TPOR and added Min value, added TBPIICCK and TSPIICCK. Also in Table 46, added device dependencies to FSMCCK and FRBCCK. Updated and added data to Table 61 through Table 75, and Table 78. In Table 76, added data on the XC6SLX45-FG(G)676 and revised the XC6SLX45T and XC6SLX150T values. The following changes to this specification are addressed in the product change notice XCN10024, MCB Performance and JTAG Revision Code for Spartan-6 LX16 and LX45 FPGAs. In Table 2, revised the VCCINT to add the memory controller block extended performance specifications. In Table 25, changed the standard specifications and added extended performance specifications for the memory controller block and note 2. Added Note 4 and updated values in Table 33.
06/24/10
1.6
Production release of XC6SLX45T (-2 and -3 speed grades), XC6SLX16 and XC6SLX45 (-3 speed grade) devices which includes changes to Table 26 and Table 27 (ISE v12.1 software with speed specification v1.08). Added the -3N speed grade, which designates Spartan-6 devices that do not support MCB functionality (specifications are identical to the -3 speed grade). This includes changes to Table 2 (note 2), Table 25 (note 4), and Switching Characteristics (Table 26). Updated Simultaneously Switching Outputs discussion. Added -3 speed grade values for TTAP and FMINCAL values in Table 38. In Table 39, updated TRPW (-2 and -3 speed grade) values and FTOG (-3 speed grade) values. In Table 47, updated TGIO (-2 and -3 speed grade) values. Updated -3 values in spread spectrum section of Table 55. Production release of specific devices listed in Table 26 and Table 27 using ISE v12.2 software with speed specification v1.11. Added Note 3 advising designers of the patch which contains v1.11. Also updated the -1L speed specification to v1.04. Updated numerous -4 and -1L values. Added -4 TTAP values and FMINCAL to Table 38. Revised TCINCK/TCKCIN in Table 39. In Table 40, revised TSHCKO. In Table 41, revised TREG. Added new -1L values to Table 46. Added and updated values in Table 76. Production release of XC6SLX25, XC6SLX25T, XC6SLX100 and XC6SLX100T in the specific speed grades listed in Table 26 and Table 27 using ISE v12.2 software with speed specification v1.11. Added note 7 to Table 2 and moved VFS and RFUSE to a new Table 3. Added IHS and Note 4 to Table 4. Added note 1 to Table 28. Added and updated SSO limits per VCCO/GND pairs in Table 33. Added note 3 to Table 46. In Table 52, removed -1L specifications for CLKOUT_PER_JITT_DV1/2 and revised CLKIN_CLKFB_PHASE and CLKOUT_PHASE_DLL values. Updated note 3 in both Table 54 and Table 55. Updated values for FGTPRANGE1, FGTPRANGE2, and FGPLLMIN in Table 18. Revised -3 and -4 values in Table 21. Removed the -1L speed grade readback support restriction and Note 3 in Table 46.
07/16/10
1.7
07/26/10
1.8
08/23/10
1.9
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS.
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